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h c 05 MC68HC05L28/d MC68HC05L28 mc68hc705l28 technical data MC68HC05L28 technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
1 2 3 4 5 6 7 8 9 10 11 12 13 14 a tpg 1 introduction modes of operation and pin descriptions memory and registers input/output ports core timer 16-bit programmable timer liquid crystal display driver module i 2 c-bus a/d converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information mc68hc705l28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 mc68hc705l28 high-density complementary metal oxide semiconductor (hcmos) microcontroller unit tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
tpg conventions where ab bre viations are used in the te xt, an e xplanation can be f ound in the glossary, at the back of this manual. register and bit mnemonics are de?ned in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset. unless otherwise stated, shaded cells in a register diag r am indicate that the bit is either unused or reserved; u is used to indicate an unde?ned state (on reset). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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MC68HC05L28 motorola i table of contents paragraph number page number title table of contents 1 introduction 1.1 features................................................................................................................ 1-1 1.2 mask options on the MC68HC05L28.................................................................... 1-3 1.2.1 option register (opt)...................................................................................... 1-3 2 modes of operation and pin descriptions 2.1 modes of operation ............................................................................................... 2-1 2.1.1 MC68HC05L28 modes of operation................................................................ 2-2 2.1.1.1 single chip mode....................................................................................... 2-2 2.1.1.2 ram bootloader mode .............................................................................. 2-2 2.1.2 mc68hc705l28 modes of operation .............................................................. 2-4 2.1.2.1 eprom bootloader mode ......................................................................... 2-4 2.1.2.2 ram bootloader mode .............................................................................. 2-4 2.2 pin descriptions .................................................................................................... 2-6 2.2.1 vdd and vss ................................................................................................. 2-6 2.2.2 irq0 ............................................................................................................... 2-6 2.2.3 irq1................................................................................................................ 2-6 2.2.4 irq2................................................................................................................ 2-6 2.2.5 osc1, osc2 .................................................................................................. 2-7 2.2.5.1 crystal ....................................................................................................... 2-8 2.2.5.2 external clock ............................................................................................ 2-8 2.2.6 reset............................................................................................................ 2-8 2.2.7 pa0 C pa7, pb0 C pb7.................................................................................... 2-9 2.2.8 pd0 C pd5 ...................................................................................................... 2-9 2.2.9 bp0 C bp3, fp0 C fp17 ................................................................................. 2-9 2.2.10 ad0 C ad1, vrefh/vrefl ........................................................................... 2-9 2.3 low power modes................................................................................................. 2-10 2.3.1 stop .............................................................................................................. 2-10 2.3.2 wait ............................................................................................................... 2-12 2.3.3 data retention ................................................................................................. 2-12 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola ii MC68HC05L28 table of contents paragraph number page number title 3 memory and registers 3.1 registers ...............................................................................................................3-1 3.2 lcd ram ..............................................................................................................3-1 3.3 ram.......................................................................................................................3-1 3.4 programming registers ..........................................................................................3-3 3.4.1 eeprom programming register (eeprog)....................................................3-3 3.4.1.1 cpen charge pump enable ..................................................................3-3 3.4.1.2 er1, er0 erase select bits ...................................................................3-3 3.4.1.3 latch eeprom latch control ..............................................................3-4 3.4.1.4 eerc eeprom rc oscillator control ...................................................3-4 3.4.1.5 eepgm eeprom program control .......................................................3-4 3.4.2 eprom programming register (pcr)..............................................................3-4 3.4.2.1 elat eprom latch control....................................................................3-5 3.4.2.2 pgm eprom program control ..............................................................3-5 4 input/output ports 4.1 input/output programming .....................................................................................4-1 4.2 ports a and b ........................................................................................................4-2 4.3 port d ....................................................................................................................4-2 4.4 port registers .........................................................................................................4-3 4.4.1 port data registers (porta, portb and portd) .........................................4-3 4.4.2 data direction registers (ddra, ddrb and ddrd)........................................4-3 4.4.3 port d control register (cond) ........................................................................4-4 4.4.4 port d select register (seld)...........................................................................4-4 5 core timer 5.1 real time interrupts (rti) ......................................................................................5-2 5.2 computer operating properly (cop) watchdog timer ............................................5-3 5.3 core timer registers ...............................................................................................5-3 5.3.1 core timer control and status register (ctcsr) ..............................................5-3 5.3.2 core timer counter register (ctcr).................................................................5-5 5.4 core timer during wait .........................................................................................5-5 5.5 core timer during stop ........................................................................................5-5 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola iii table of contents paragraph number page number title 6 16-bit programmable timer 6.1 counter ................................................................................................................. 6-3 6.1.1 counter high register counter low register alternate counter high register alternate counter low register ......................................................................... 6-3 6.2 timer functions ..................................................................................................... 6-4 6.2.1 timer control registers .................................................................................... 6-4 6.2.1.1 timer control register 1 (tcr1)................................................................. 6-4 6.2.1.2 timer control register 2 (tcr2)................................................................. 6-6 6.2.2 timer status register (tsr)............................................................................. 6-7 6.2.3 input capture registers .................................................................................... 6-9 6.2.3.1 input capture register 1 ............................................................................. 6-9 6.2.3.2 input capture register 2 ............................................................................. 6-10 6.2.4 output compare registers ............................................................................... 6-11 6.2.4.1 output compare register 1......................................................................... 6-11 6.2.4.2 output compare register 2......................................................................... 6-12 6.3 timer during wait mode...................................................................................... 6-13 6.4 timer during stop mode..................................................................................... 6-13 6.5 timer state diagrams ............................................................................................ 6-13 7 liquid crystal display driver module 7.1 lcd ram.............................................................................................................. 7-2 7.2 lcd operation....................................................................................................... 7-2 7.3 timing signals and lcd voltage waveforms ......................................................... 7-3 7.4 lcd control register.............................................................................................. 7-8 7.5 lcd during wait mode........................................................................................ 7-8 8 i 2 c-bus 8.1 i 2 c-bus features.................................................................................................... 8-1 8.2 i 2 c-bus system con?guration................................................................................ 8-2 8.3 i 2 c-bus protocol.................................................................................................... 8-2 8.3.1 start signal .................................................................................................. 8-2 8.3.2 transmission of the slave address .................................................................. 8-2 8.3.3 data transfer ................................................................................................... 8-4 8.3.4 stop signal .................................................................................................... 8-4 8.3.5 repeated start signal.................................................................................. 8-4 8.3.6 arbitration procedure ...................................................................................... 8-4 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola iv MC68HC05L28 table of contents paragraph number page number title 8.3.7 clock synchronization ......................................................................................8-5 8.3.8 handshaking....................................................................................................8-5 8.4 registers ...............................................................................................................8-6 8.4.1 i 2 c-bus address register (madr) ....................................................................8-6 8.4.2 i 2 c-bus frequency divider register (fdr).........................................................8-6 8.4.3 i 2 c-bus control register (mcr) ........................................................................8-7 8.4.4 i 2 c-bus status register (msr)..........................................................................8-8 8.4.5 i 2 c-bus data register (mdr) ............................................................................8-10 8.5 programming .........................................................................................................8-10 8.5.1 initialization ......................................................................................................8-10 8.5.2 start signal and the ?rst byte of data............................................................8-10 8.5.3 software response ...........................................................................................8-11 8.5.4 generation of a stop signal ...........................................................................8-12 8.5.5 generation of a repeated start signal ..........................................................8-12 8.5.6 slave mode ......................................................................................................8-13 8.5.7 arbitration lost ..................................................................................................8-13 8.5.8 operation during stop and wait modes.......................................................8-13 9 a/d converter 9.1 a/d converter operation.........................................................................................9-1 9.2 a/d registers..........................................................................................................9-3 9.2.1 a/d status/control register (adstat)...............................................................9-3 9.2.1.1 coco conversion complete ?ag ..........................................................9-3 9.2.1.2 adrc a/d rc oscillator control ............................................................9-3 9.2.1.3 adon a/d converter on ........................................................................9-3 9.2.1.4 ch3 C ch0 a/d channels 3, 2, 1 and 0.................................................9-4 9.2.2 a/d input register (adin) .................................................................................9-5 9.2.3 a/d result data register (addata) ...................................................................9-5 9.3 adx analog input ...................................................................................................9-6 10 resets and interrupts 10.1 resets .................................................................................................................10-1 10.1.1 power-on reset...............................................................................................10-1 10.1.2 reset pin .....................................................................................................10-1 10.1.3 computer operating properly (cop) reset .....................................................10-2 10.2 interrupts .............................................................................................................10-2 10.2.1 non-maskable software interrupt (swi).........................................................10-3 10.2.2 maskable hardware interrupts........................................................................10-3 10.2.2.1 external interrupt ( irq0, irq1, irq2) .....................................................10-5 10.2.2.2 real time and core timer (ctimer) interrupts.........................................10-7 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola v table of contents paragraph number page number title 10.2.2.3 programmable 16-bit timer interrupt........................................................ 10-7 10.2.2.4 i 2 c interrupts .......................................................................................... 10-8 10.2.3 hardware controlled interrupt sequence ....................................................... 10-8 11 cpu core and instruction set 11.1 registers............................................................................................................. 11-1 11.1.1 accumulator (a) ............................................................................................ 11-1 11.1.2 index register (x)........................................................................................... 11-2 11.1.3 program counter (pc) ................................................................................... 11-2 11.1.4 stack pointer (sp) ......................................................................................... 11-2 11.1.5 condition code register (ccr) ...................................................................... 11-2 11.2 instruction set ..................................................................................................... 11-3 11.2.1 register/memory instructions ....................................................................... 11-4 11.2.2 branch instructions ....................................................................................... 11-4 11.2.3 bit manipulation instructions ......................................................................... 11-4 11.2.4 read/modify/write instructions ...................................................................... 11-4 11.2.5 control instructions ....................................................................................... 11-4 11.2.6 tables............................................................................................................ 11-4 11.3 addressing modes .............................................................................................. 11-11 11.3.1 inherent......................................................................................................... 11-11 11.3.2 immediate ..................................................................................................... 11-11 11.3.3 direct............................................................................................................. 11-11 11.3.4 extended....................................................................................................... 11-12 11.3.5 indexed, no offset.......................................................................................... 11-12 11.3.6 indexed, 8-bit offset....................................................................................... 11-12 11.3.7 indexed, 16-bit offset..................................................................................... 11-12 11.3.8 relative ......................................................................................................... 11-13 11.3.9 bit set/clear ................................................................................................... 11-13 11.3.10 bit test and branch ........................................................................................ 11-13 12 electrical specifications 12.1 maximum ratings ................................................................................................ 12-1 12.2 thermal characteristics and power considerations............................................. 12-2 12.3 dc electrical characteristics for 5v operation..................................................... 12-3 12.4 ac electrical characteristics for 5v operation ..................................................... 12-4 12.5 a/d converter characteristics.............................................................................. 12-5 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola vi MC68HC05L28 table of contents paragraph number page number title 13 mechanical data 13.1 pin con?gurations 56-pin sdip .......................................................................13-1 13.2 mechanical dimensions 56-pin plastic shrink dual-in-line (sdip) ...................13-2 14 ordering information 14.1 eprom ...............................................................................................................14-1 14.2 veri?cation media ................................................................................................14-1 14.3 rom veri?cation units (rvu)...............................................................................14-2 a mc68hc705l28 a.1 features ............................................................................................................... a-1 a.2 modes of operation............................................................................................... a-1 a.2.1 single chip mode ............................................................................................ a-2 a.2.2 eprom bootloader mode............................................................................... a-2 a.2.3 ram bootloader mode .................................................................................... a-4 a.3 vpp ...................................................................................................................... a-4 a.4 eprom programming register (pcr) .................................................................. a-5 a.4.1 elat eprom latch control ........................................................................ a-5 a.4.2 pgm eprom program control................................................................... a-5 a.5 pin con?gurations 56-pin sdip ........................................................................ a-6 a.6 ordering information............................................................................................. a-6 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola vii list of figures figure number page number title list of figures 1-1 MC68HC05L28/ mc68hc705l28 block diagram....................................................1-2 2-1 ram bootloader circuit ...........................................................................................2-3 2-2 mc68hc705l28 eprom programming circuit ......................................................2-5 2-3 oscillator connections ............................................................................................2-7 2-4 rc connection for external por ............................................................................2-8 2-5 stop ?owchart ......................................................................................................2-11 2-6 wait ?owchart .......................................................................................................2-13 3-1 memory map of the MC68HC05L28 and mc68hc705l28 ....................................3-2 4-1 standard i/o port structure.....................................................................................4-2 5-1 core timer block diagram........................................................................................5-1 6-1 16-bit programmable timer block diagram ..............................................................6-2 6-2 timer state timing diagram for reset .......................................................................6-14 6-3 timer state timing diagram for input capture ..........................................................6-14 6-4 timer state timing diagram for output compare ......................................................6-15 6-5 timer state timing diagram for timer over?ow.........................................................6-15 7-1 lcd system block diagram.....................................................................................7-1 7-2 voltage level selection ............................................................................................7-3 7-3 lcd waveform with 2 backplanes, 1/2 bias ............................................................7-4 7-4 lcd waveform with 2 backplanes, 1/3 bias ............................................................7-5 7-5 lcd waveform with 3 backplanes...........................................................................7-6 7-6 lcd waveform with 4 backplanes...........................................................................7-7 8-1 i 2 c bus transmission signal diagrams ....................................................................8-3 8-2 clock synchronization.............................................................................................8-5 8-3 example of a typical i 2 c-bus interrupt routine ........................................................8-14 9-1 a/d converter block diagram ..................................................................................9-2 9-2 electrical model of an a/d input pin........................................................................9-6 10-1 interrupt ?ow chart................................................................................................10-4 11-1 programming model .............................................................................................11-1 11-2 stacking order ......................................................................................................11-2 12-1 equivalent test load ..............................................................................................12-2 13-1 56-pin sdip pinout for the MC68HC05L28/ mc68hc705l28...............................13-1 13-2 mechanical dimensions for 56-pin sdip...............................................................13-2 a-1 mc68hc705l28 eprom programming circuit ..................................................... a-3 a-2 56-pin sdip pinout for the mc68hc705l28.......................................................... a-6 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola viii MC68HC05L28 list of figures this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola ix list of tables table number page number title list of tables 2-1 MC68HC05L28 operating mode entry conditions...................................................2-1 2-2 mc68hc705l28 operating mode entry conditions.................................................2-1 2-3 ram bootloader mode jump vector (MC68HC05L28) ............................................2-3 2-4 ram bootloader mode jump vectors (mc68hc705l28) ........................................2-3 3-1 erase mode select..................................................................................................3-3 3-2 register outline.......................................................................................................3-6 4-1 i/o pin states ..........................................................................................................4-1 4-2 i/o con?guration functions......................................................................................4-4 5-1 minimum cop reset times......................................................................................5-3 5-2 example rti periods ..............................................................................................5-4 7-1 lcd ram organization...........................................................................................7-2 7-2 multiplex ratio/backplane selection .........................................................................7-8 8-1 i 2 c-bus prescaler....................................................................................................8-7 9-1 a/d clock selection .................................................................................................9-4 9-2 a/d channel assignment.........................................................................................9-4 10-1 interrupt priorities .................................................................................................10-3 10-2 irq1 interrupt sensitivity ......................................................................................10-6 10-3 irq2 interrupt sensitivity ......................................................................................10-7 11-1 mul instruction.....................................................................................................11-5 11-2 register/memory instructions...............................................................................11-5 11-3 branch instructions ...............................................................................................11-6 11-4 bit manipulation instructions.................................................................................11-6 11-5 read/modify/write instructions .............................................................................11-7 11-6 control instructions...............................................................................................11-7 11-7 instruction set .......................................................................................................11-8 11-8 m68hc05 opcode map.........................................................................................11-10 12-1 maximum ratings ..................................................................................................12-1 12-2 package thermal characteristics...........................................................................12-2 12-3 dc electrical characteristics .................................................................................12-3 12-4 control timing .......................................................................................................12-4 12-5 a/d converter characteristics................................................................................12-5 14-1 mc order numbers................................................................................................14-1 a-1 mc68hc705l28 operating mode entry conditions................................................ a-1 a-2 mc68hc705l28 bootloader mode jump vectors................................................... a-4 a-3 mc68hc705l28 order numbers ........................................................................... a-6 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola x MC68HC05L28 list of tables this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 1-1 introduction 1 1 introduction the MC68HC05L28 is a ?e xib le gener al-pur pose microcomputer , par ticular ly suited to applications throughout the consumer and automotiv e industr ies . it is a member of the highly successful motorola m68hc05 f amily of microcomputers and includes man y of the standard features of this family. its hardware includes 8k of rom, 240 bytes of eeprom and 256 bytes of ram, plus a multi-master i 2 c interface, an a/d converter and an lcd driver subsystem. the lcd subsystem is par ticular ly ?e xib le and can be prog r ammed to dr iv e a wide r ange of industr y-standard lcd de vices making the MC68HC05L28 par ticular ly suited to man y applications in radio, tv and compact disc systems. the MC68HC05L28s communications , a/d and lcd modules and its tw o timer modules provide the perf ect combination f or car dashboard applications , where analog signals from speed and distance sensors have to be converted to digital signals before being processed and displayed. the mc68hc705l28 is an epr om equivalent v ersion of the MC68HC05L28, with 8k of epr om instead of 8k of r om. all ref erences to the MC68HC05L28 apply equally to the mc68hc705l28, unless otherwise noted. ref erences speci?c to the mc68hc705l28 are italiciz ed in the text and also, for quick reference, they are summarised in appendix a. 1.1 features ? fully static chip design featuring the industry standard m68hc05 core ? multi-master i 2 c-bus ? communication port ? 8176 bytes of user rom (MC68HC05L28); 8128 bytes of user eprom (mc68hc705l28) ? 240 bytes of eeprom ? 240 bytes of bootstrap rom ? 256 bytes of ram ? i 2 c-bus is a proprietary philips interface bus tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 1-2 MC68HC05L28 introduction 1 ? lcd subsystem with 18 frontplanes and 4 backplanes ? 16-bit programmable timer with 2 input capture and 2 output compare functions ? 15-stage, multifunctional core timer, with over?ow, real-time interr upt and computer oper ating properly (cop) watchdog timer (software selectable) ? 3 interrupt request pins with edge or edge-and-level sensitive triggering (software selectable) ? 2-channel, 8-bit analog-to-digital converter ? 16 dedicated i/o lines 6 i/o lines shared with the 16-bit programmable timer and the multi-master i 2 c-bus interface ? power saving stop and wait modes ? available in 56-pin sdip package figure 1-1 MC68HC05L28/ mc68hc705l28 block diagram cop system bp1 bp0 fp17 fp16 fp15 fp14 fp13 fp12 fp11 fp9 fp8 fp7 fp6 fp5 fp4 fp3 fp2 fp1 fp0 fp10 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 ad0 ad1 vrefl vrefh port d oscillator 240 x 8 240 x 8 osc1 osc2 reset irq0 irq1 irq2 vdd vss 16-bit 18 x 4 lcd subsystem m68hc05 cpu 256 x 8 ram 8176 x 8 user rom port b port a pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pd0 pd1 pd2 pd3 pd4 pd5 bp2 bp3 tcmp2 tcap2 tcmp1 tcap1 scl0 sda0 8128 x 8 user eprom or core timer timer bootstrap rom i 2 c eeprom 8-bit, 2-channel a/d converter tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 1-3 introduction 1 1.2 mask options on the MC68HC05L28 there is only one mask option on the MC68HC05L28. this is to enab le or disab le the st op instruction. it is programmed during manufacture and must be speci?ed on the order form. 1.2.1 option register (opt) in addition to its mask option, the MC68HC05L28 also has tw o functions that are prog rammable via an options register (opt). this register can be wr itten to once after a reset, b ut it can be read at any time. irqed irq edge sensitivity this bit selects the irq0 sensitivity. 1 (set) C the irq0 is edge-sensitive. 0 (clear) C the irq0 is edge-and-level-sensitive. reset clears this bit. copon cop function enable/disable 1 (set) C this bit enables the cop watchdog. 0 (clear) C this bit disables the operation of the cop. reset clears this bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset option register (opt) $001d irqed copon ???? ?100 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 1-4 MC68HC05L28 introduction 1 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-1 modes of operation and pin descriptions 2 2 modes of operation and pin descriptions 2.1 modes of operation the MC68HC05L28 has tw o modes of oper ation a vailab le to the user C single chip and ram bootloader. the mc68hc705l28 also has tw o modes of oper ation C single chip and epr om/ram bootloader . t able 2-1 and t able 2-2 sho w the conditions required to enter each mode on the rising edge of reset. table 2-1 MC68HC05L28 operating mode entry conditions irq0/vpp pb2 pb3 pb6 mode v ss to v dd x x x single chip 2 x v dd 1 0 v dd ram bootloader jump to ram ($81) 2 x v dd 1 1 v dd load/execute ram table 2-2 mc68hc705l28 operating mode entry conditions irq0/vpp pb2 pb3 pb6 mode v ss to v dd x x x single chip 2 x v dd 0 0 v dd eprom bootloader verify only 2 x v dd 0 1 v dd program/verify 2 x v dd 1 0 v dd ram bootloader jump to ram ($81) 2 x v dd 1 1 v dd load/execute ram tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-2 MC68HC05L28 modes of operation and pin descriptions 2 2.1.1 MC68HC05L28 modes of operation 2.1.1.1 single chip mode this is the normal oper ating mode of the MC68HC05L28 and the mc68hc705l28. in this mode the de vice functions as a self-contained microcomputer (mcu) with all on-board per ipherals, including tw o 8-bit i/o por ts and one 6-bit i/o por t, a vailab le to the user . all address and data activity occurs within the mcu. single chip mode is entered on the r ising edge of reset if the v oltage lev el on the irq0 pin is within the normal operating range. warning: in the mc68hc705l28, all v ectors are f etched from epr om in single chip mode; therefore , the epr om m ust be prog r ammed (via the bootloader mode) bef ore the device is powered up in single chip mode. 2.1.1.2 ram bootloader mode the ram bootloader mode f or the MC68HC05L28 and mc68hc705l28 allo ws the user to perform simple load and execute instructions in ram. to make use of this feature a circuit board should be constr ucted as sho wn in figure 2-1. correct con?gur ation of por t pins pb2 and pb3 enables loading of a user program into ram for execution. the ram bootloader is selected when the de vice is put into bootloader mode with pb2 held high. if pb3 is low, the progr am counter is set to $0081 and a pre viously loaded ram program can be ex ecuted. if pb3 is high at reset a prog r am is ser ially loaded from p a0 into the ram and e xecuted from $0081. the ?rst byte to be loaded is the count byte which should hold the program length plus the count byte. therefore, for a progr am length of $30, the count should equal $31. the maxim um program size , including the count b yte i s 254 b ytes ($fe), as t w o b ytes m ust be left f or the stac k dur ing download. the format of data f or the ram bootloader mode is 9600 baud, 8-bit, no par ity, 1 start, 1stop (for 2 mhz bus speed). in the ram bootloader mode interr upt v ectors are mapped to pseudo-v ectors in ram (f or MC68HC05L28 v ectors see t able 2-4 and f or mc68hc705l28 v ectors seetable 2-4 ). this allo ws progr ammers to use their o wn ser vice-routine addresses . each pseudo-v ector is allo w ed three b ytes of space , r ather than the tw o b ytes f or nor mal v ectors , because an e xplicit jump (jmp) opcode is needed to cause the desired jump to the users service-routine address. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-3 modes of operation and pin descriptions 2 figure 2-1 ram bootloader circuit table 2-3 ram bootloader mode jump vector (MC68HC05L28) address pseudo-vector 0084 software interrupt table 2-4 ram bootloader mode jump vectors (mc68hc705l28) address pseudo-vector 0083 software interrupt 0086 irq 0089 core timer 008c i 2 c-bus 008f programmable timer pa0 pb2 pb3 irq/vpp osc1 osc2 vdd reset vss 2 x v dd rxd 4.0 mhz v dd v dd 100nf 100nf 22pf 22pf pb 3 function 0 jump to ram ($81) 1 load/execute ram MC68HC05L28 all resistors are 10 k? unless speci?ed otherwise 10 m? pb6 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-4 MC68HC05L28 modes of operation and pin descriptions 2 2.1.2 mc68hc705l28 modes of operation 2.1.2.1 eprom bootloader mode this mode is used f or progr amming the on-board epr om. in bootloader mode the oper ation of the de vice is the same as in single chip mode , e xcept that the v ectors are f etched from a reser ved area of r om at locations $3fe4 to $3fef , instead of the epr om. the pin assignments are identical to that of single chip mode sho wn earlier . a recommended prog r amming circuit is sho wn in figure 2-2. because the addresses in the mc68hc705l28 and the epr om containing the user code are incremented independently , it is essential that the data la y out in the 27128 epr om conf orms e xactly to the mc68hc705l28 memor y map . the bootloader uses an e xter nal 14-bit counter to address the memory de vice containing the code to be copied. this counter requires a cloc k and a reset function which are provided by the mc68hc705l28. in this mode all interr upt v ectors are mapped to pseudo-v ectors in ram (see t able 2-4). this allows progr ammers to use their o wn ser vice routine addresses . each pseudo-v ector is allo wed three b ytes of space , r ather than the tw o bytes for normal vectors , because an e xplicit jump (jmp) opcode is needed to cause the desired jump to the users service routine address. the bootloader code deals with the cop ying of user code from an e xter nal epr om into the on-chip epr om. the bootloader function can only be used with an e xter nal epr om. the bootloader performs a programming pass followed by a verify pass. pins pb2 and pb3 are used to select v ar ious bootloader functions , including the prog ramming mode (see figure 2-2). tw o other pins , pb1 and pb6 are used to dr iv e the pr og and verf led outputs. while the eprom is being programmed the pr og led lights up; when prog ramming is complete the internal eprom contents are compared to that of the external eprom and, if they match exactly, the verf led lights up. when ?nished programming, the prog leg turns off. if the mc68hc705l28 memor y contents are the same as the epr om the verf led lights up , otherwise no leds are turned on. note: the eprom must be erased before performing a program cycle. 2.1.2.2 ram bootloader mode see section 2.1.1.2. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-5 modes of operation and pin descriptions 2 figure 2-2 mc68hc705l28 eprom programming circuit 470 s1 1 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 vss oe vcc pgm vpp mcm27128 (16k eprom) d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 vdd clk rst mc74hc393 vss pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb3 pb2 pb7 pb5 pb1 pb6 vrefh tcap1 vdd +5v +5v vss ocs2 ocs1 +5v 10k +5v 10k +5v 10k +5v 10k s3 vrefl adin s2 s1 tcap2 irq0/vpp vpp l1 clock clear l1 = verify l2 = program s2 0 0 function program/verify verify only reset 470 l2 +5v +5v +5v mc68hc705l28 4 mhz 22pf 22pf 10 m? ce tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-6 MC68HC05L28 modes of operation and pin descriptions 2 2.2 pin descriptions pin assignments are shown in section 13. 2.2.1 vdd and vss pow er is supplied to the microcontroller using these tw o pins . vdd is the positiv e supply and vss is ground. it is in the nature of cmos designs that v ery fast signal tr ansitions occur on the mcu pins . these short rise and fall times place very high short-dur ation current demands on the po wer supply. to prev ent noise prob lems , special care m ust be tak en to pro vide good po w er supply b ypassing at the mcu. bypass capacitors should have good high-frequency character istics and be as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 2.2.2 irq 0 this interr upt has a softw are option which off ers tw o types of interr upt tr igger ing sensitivity . it contains an internal schmitt trigger as part of its input to improve noise immunity. 2.2.3 irq1 this interr upt has a softw are option which off ers f our types of interr upt tr igger ing sensitivity . it contains an inter nal schmitt tr igger as par t of its input to impro v e noise imm unity . this interr upt can be enabled/disabled independently. 2.2.4 irq2 this interr upt has a softw are option which off ers f our types of interr upt tr igger ing sensitivity . it contains an inter nal schmitt tr igger as par t of its input to impro v e noise imm unity . this interr upt can be enabled/disabled independently. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-7 modes of operation and pin descriptions 2 2.2.5 osc1, osc2 these pins pro vide control input f or an on-chip oscillator circuit. a cr ystal connected to these pins supplies the oscillator cloc k. the oscillator frequency (f osc ) is divided by two to give the internal bus frequency (f op ). figure 2-3 oscillator connections osc1 osc2 r p mcu c osc2 c osc1 osc1 osc2 mcu nc external clock osc1 osc2 r s c 1 l c 0 crystal 2 mhz 4 mhz unit r s (max) 400 75 c 0 5 7 pf c 1 8 12 nf c osc1 15 C 40 15 C 30 pf c osc2 15 C 30 15 C 25 pf r p 10 10 m? q 30 000 40 000 (d) crystal parameters (c) external clock source connections (b) crystal equivalent circuit (a) crystal oscillator connections tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-8 MC68HC05L28 modes of operation and pin descriptions 2 2.2.5.1 crystal the circuit shown in figure 2-3(a) is recommended when using a cr ystal . figure 2-3(d) lists the recommended capacitance and f eedback resistance values. the inter nal oscillator is designed to interf ace with an a t-cut parallel-resonant quartz cr ystal resonator in the frequency r ange speci?ed for f osc (see section 12.4). use of an e xter nal cmos oscillator is recommended when cr ystals outside the speci?ed r anges are to be used. the cr ystal and associated components should be mounted as close as possib le to the input pins to minimiz e output distor tion and star t-up stabilization time . the man uf acturer of the par ticular cr ystal being considered should be consulted for speci?c information. 2.2.5.2 external clock an external cloc k should be applied to the osc1 input, with the osc2 pin left unconnected, as shown in figure 2-3(c). the t oxov speci?cation (see section 12.4) does not apply when using an external cloc k input. the equiv alent speci?cation of the e xternal cloc k source should be used in lieu of t oxov . 2.2.6 reset this activ e lo w input pin is used to reset the mcu . applying a logic z ero to this pin f orces the de vice to a kno wn star t-up state . this input has an inter nal schmitt tr igger to impro v e noise immunity. the mcu has its o wn inter nal po w er-on reset (por) circuit. if , ho wever , the user requires an additional por, then an rc netw or k can be connected to this pin as sho wn in figure 2-4. the user m ust ensure that the rc time constant of this netw or k is g reater than the the oscillator stabilization period. a time constant of at least 100 ms is recommended. figure 2-4 rc connection for external por reset MC68HC05L28 v dd v ss r c tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-9 modes of operation and pin descriptions 2 2.2.7 pa0 C pa7, pb0 C pb7 these 16 i/o lines compr ise por ts a and b . the state of an y pin is softw are programmable, and all the pins are con?gured as inputs dur ing pow er-on or reset. p or t b pins in output mode can sink 10ma of current to drive the leds. 2.2.8 pd0 C pd5 these six i/o lines compr ise port d . the state of an y pin is softw are programmable , and all the pins are con?gured as inputs dur ing po w er-on or reset. this por t shares its pins with the 16-bit timer and i 2 c subsystems . there are f our read/wr ite registers associated with the por t to select the diff erent functions . all the por t bits can be con?gured as input/output pins or used b y other systems within the mcu. this 6-bit i/o por t shares its pins with other subsystems on the mcu and is controlled using the por t d control (cond) and select (seld) registers . on reset, all registers e xcept the data register are cleared thereb y con?gur ing all por t pins as nor mal inputs with pull-up resistors . wr iting a 1 to any bit in cond connects the subsystem function to the corresponding port d pin. 2.2.9 bp0 C bp3, fp0 C fp17 these signals compr ise the lcd dr iv er subsystem. the subsystem has a maxim um of 18 frontplanes and four backplanes. 2.2.10 ad0 C ad1, vrefh/vrefl these 4 signals compr ise the a-to-d interf ace . the subsystem has a maxim um of tw o a/d channels. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-10 MC68HC05L28 modes of operation and pin descriptions 2 2.3 low power modes 2.3.1 stop the stop instr uction places the mcu in its lo west pow er consumption mode . in st op mode, the inter nal oscillator is tur ned off , halting all inter nal processing, including timer (and cop w atchdog timer) operation. during the stop mode, the core timer interrupt ?ags (ctof and rtif) and interrupt enable bits (ct ofe and r tie) in the ctcsr are cleared b y internal hardware . this remo ves any pending timer interr upt requests and disab les an y fur ther timer interr upts . the timer prescaler is also cleared. the i-bit in the ccr is cleared to enab le e xter nal interr upts . all other registers , the remaining bits in the ctcsr, and memor y contents remain unaltered. all input/output lines remain unchanged. the processor can be brought out of the st op mode only b y an e xternal interrupt or a reset (see figure 2-5). the stop instr uction can be disab led b y a mask option. when disab led, it is e x ecuted as a nop . tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-11 modes of operation and pin descriptions 2 figure 2-5 stop ?owchart turn on oscillator wait for time delay to stabilize stop oscillator and all clocks clear i-bit reset external interrupt ( irq0,1,2) stop no yes no yes 1. fetch reset vector or 2. service interrupt: a. stack b. set i-bit c. vector to interrupt routine tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-12 MC68HC05L28 modes of operation and pin descriptions 2 2.3.2 wait the w ait instr uction places the mcu in a lo w po w er consumption mode , b ut the w ait mode consumes more po w er than the st op mode . all cpu action is suspended, b ut the core timer , 16-bit timer and i 2 c remains activ e . an interr upt from the core timer , 16-bit timer or i 2 c (if enab led) will cause the mcu to exit wait mode. dur ing w ait mode , the i-bit in the ccr is cleared to enab le interr upts . all other registers , memor y and input/output lines remain in their pre vious state . the core timer ma y be enab led to allo w a periodic exit from the wait mode (see figure 2-6). 2.3.3 data retention the contents of the ram are retained at supply v oltages as lo w as 2.0vdc. this is called the data retention mode, in which data is maintained but the device is not guaranteed to operate. for lowest power consumption in data retention mode the device should be put into stop mode bef ore reducing the supply v oltage , to ensure that all the cloc ks are stopped. if the de vice is not in st op mode then it is recommended that reset be held lo w while the po w er supply is outside the normal operating range, to ensure that processing is suspended in an orderly manner. recover y from data retention mode , after the po w er supply has been restored, is b y pulling the reset line high. to put the mcu into data retention mode: ? set reset pin to zero ? reduce the voltage on vdd. reset must remain low during data retention mode to take the mcu out of data retention: ? return vdd to normal operating level ? return reset to logical one. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 2-13 modes of operation and pin descriptions 2 figure 2-6 wait ?owchart reset oscillator active timer clock active processor clocks stopped external interrupt ( irq0,1,2) ctimer internal interrupt restart processor clock wait yes no yes no no yes 1. fetch reset vector or 2. service interrupt: a. stack b. set i-bit c. vector to interrupt routine tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2-14 MC68HC05L28 modes of operation and pin descriptions 2 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 3-1 memory and registers 3 3 memory and registers the MC68HC05L28 has a 16k byte memor y map consisting of registers , user rom, user ram, bootstrap rom, lcd ram, eeprom and i/o, as shown in figure 3-1. 3.1 registers all the i/o , control and status registers of the MC68HC05L28 are contained within the ?rst 64-b yte block of the memory map (address $0000 to $003f). 3.2 lcd ram the 12 b ytes of lcd ram are located at address $0040 to $004b . this ram is used to store the data needed for the lcd. see section 7.1 for further details of the organization of these bits. 3.3 ram the user ram consists of 256 b ytes of memor y , from $0080 to $017f . this is shared with a 64 byte stack area. the stack begins at $00ff and counts down to $00c0. note: using the stac k area f or data stor age or tempor ar y w or k locations requires care to prev ent the data from being o verwr itten due to stac king from an interr upt or subroutine call. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 3-2 MC68HC05L28 memory and registers 3 figure 3-1 memory map of the MC68HC05L28 and mc68hc705l28 user rom (8176 bytes) user vectors (16 bytes) $0000 lcd ram i/o (64 bytes) $0040 $0080 $00c0 $0180 $3ff0 $3fff reserved stack ram (256 bytes) reserved $0300 $1000 $3f00 (12 bytes) reserved $004c eeprom (240 bytes) $03f0 reserved bootstrap rom (240 bytes) & bootstrap vectors user eprom (8128bytes) $2fc0/ $2ff0 $00ff port a data (porta) $00 port a data (porta) $01 reserved $02 reserved $03 port a data direction (ddra) $04 port b data direction (ddrb) $05 reserved $06 reserved $07 core timer control & status (ctcsr) $08 core timer counter (ctcr) $09 irq1 $0a irq2 $0b reserved $0c $0f i 2 c address (madr) $10 i 2 c frequency divider (mfdr) $11 i 2 c control (mbcr) $12 i 2 c status (mbsr) $13 i 2 c data (mdr) $14 a/d status/control (adstat) $15 a/d input (adin) $16 a/d data (addata) $17 reserved $18 $1a eeprom program (eeprog) $1b eprom program (pcr) $1c option (opt) $1d lcd control (lcd) $1e reserved $1f input capture 1 high(ic1h) $20 input capture 1 low (ic1l) $21 output compare 1 high (oc1h) $22 output compare 1 low (oc1l) $23 input capture 2 high (ic2h) $24 input capture 2 low (ic2l) $25 output compare 2 high (oc2h) $26 output compare 2 low (oc2l) $27 timer counter high (tch) $28 timer counter low (tcl) $29 alternate counter high (ach) $2a alternate counter low (acl) $2b timer control 1 (tcr1) $2c timer control 2(tcr2) $2d timer status (tsr) $2e reserved $2f port d data (portd) $30 port d data direction (ddrd) $31 port d control (cond) $32 port d select (seld) $33 reserved $34 $3f registers tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 3-3 memory and registers 3 3.4 programming registers 3.4.1 eeprom programming register (eeprog) 3.4.1.1 cpen charge pump enable this bit enables the charge pump which produces the internal programming voltage. it is set with the la tch bit and should be disab led when not in use. the programming voltage is not available until eepgm is set. 1 (set) C charge pump is enabled. 0 (clear) C charge pump is disabled. 3.4.1.2 er1, er0 erase select bits er1 and er0 are used to select either single b yte prog r amming or one of three er ase modes: byte, block or bulk. table 3-1 sho ws the modes selected f or each bit con?guration. these bits are readable and writeable and are cleared by reset. C in byte erase mode only the selected byte is erased. C in block erase mode a 64-byte block of eeprom is erased. the eeprom memory space is divided into four 64-byte blocks ($0300C$033f, $0340C$037f, $0380C$03bf , $03c0C$03ef) and an er ase to any address within a block erases that block. C in bulk erase mode the entire 240 bytes of eeprom are erased. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom program (eeprog) $001b cpen 0 er1 er0 latch eerc eepgm ?000 0000 table 3-1 erase mode select er1 er0 mode 0 0 program 0 1 byte erase 1 0 block erase 1 1 bulk erase tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 3-4 MC68HC05L28 memory and registers 3 3.4.1.3 latch eeprom latch control 1 (set) C the eeprom address and data buses are con?gured for progr amming. this causes the address and data b uses to be latched when a write to eeprom is carried out. eepr om cannot be read if latch = 1. 0 (clear) C the eeprom address and data buses are con?gured for normal reads. 3.4.1.4 eerc eeprom rc oscillator control 1 (set) C the eeprom uses an internal rc oscillator instead of the cpu clock. after setting, wait for time t rcon to allow the rc oscillator to stabilize . it should be set b y the user when the inter nal b us frequency falls below 1.5 mhz. 0 (clear) C the eeprom uses the cpu clock. 3.4.1.5 eepgm eeprom program control 1 (set) C programming power is connected to the eeprom array. eepgm can only be set if latch is set and is automatically cleared when latch = 0. 0 (clear) C programming power is disconnected from the eeprom array. note: latch and eepgm cannot be set on the same write operation 3.4.2 eprom programming register (pcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom program (pcr) $001c elat pgm uuuu uu00 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 3-5 memory and registers 3 3.4.2.1 elat eprom latch control 1 (set) C when this bit is set to 1, the eprom address and data buses are con?gured for programming. this causes the address and data buses to be latched when a write to eprom is executed. the eprom cannot be read if it is set to 1. 0 (clear) C the eprom address and data buses are con?gured for normal reads. 3.4.2.2 pgm eprom program control 1 (set) C programming power is connected to the eprom array. the pgm can only be set if elat is set and it is automatically cleared when elat = 0. 0 (clear) C eprom address and data bus are con?gured for normal reads. note: elat and pgm cannot be set in the same write operation. take the following steps to program a byte of eprom: C apply the programming voltage v pp to the vpp pin. C set the elat bit. C write to the eprom address. C set the pgm bit for a time t prog to apply the programming voltage. C clear the elat and pgm bits. note: the erased state of the eprom is $00. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 3-6 MC68HC05L28 memory and registers 3 table 3-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unaffected port b data (portb) $0001 unaffected reserved $0002 reserved $0003 port a data direction (ddra) $0004 ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 0000 0000 port b data direction (ddrb) $0005 ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 0000 0000 reserved $0006 reserved $0007 core timer control/status (ctcsr) $0008 ctof rtif ctofe rtie rt1 rt0 0000 0011 core timer counter (ctcr) $0009 0000 0000 irq1 $000a irq1int irq1ena irq1lv irq1edg irq1rst irq1val ??00 000? irq2 $000b irq2int irq2ena irq2lv irq2edg irq2rst irq2val ??00 000? reserved $000c unaffected reserved $000d unaffected reserved $000e unaffected reserved $000f unaffected i 2 c address (madr) $0010 adr7 adr6 adr5 adr4 adr3 adr2 adr1 0000 000? i 2 c frequency divide (fdr) $0011 mbc4 mbc3 mbc2 mbc1 mbc0 ???0 0000 i 2 c control (mcr) $0012 men mien msta mtx txak mmux 0000 00?? i 2 c status (msr) $0013 mcf maas mbb mal srw mif rxak 1000 ?001 i 2 c data (mdr) $0014 trxd7 trxd6 trxd5 trxd4 trxd3 trxd2 trxd1 trxd0 uuuu uuuu a/d status control (adstat) $0015 coco adrc adon ch3 ch2 ch1 ch0 0000 0000 a/d input (adin) $0016 ad1 ad0 uuuu uuuu a/d data (addata) $0017 uuuu uuuu reserved $0018 reserved $0019 reserved $001a eeprom program (eeprog) $001b cpen er1 er0 latch eerc eepgm ?000 0000 eprom program (pcr) (1) $001c elat pgm uuuu uu00 option (opt) $001d irqed copon ???? ?100 lcd control (lcd) $001e vlcdon fdisp mux4 mux3 dison ?000 0000 reserved $001f input capture 1 high (ic1h) $0020 uuuu uuuu input capture 1 low(ic1l) $0021 uuuu uuuu output compare 1 high(oc1h) $0022 uuuu uuuu output compare 1 low (oc1l) $0023 uuuu uuuu input capture 2 high (ic2h) $0024 uuuu uuuu input capture 2 low (ic2l) $0025 uuuu uuuu output compare 2 high (oc2h) $0026 uuuu uuuu output compare 2 low (oc2l) $0027 uuuu uuuu tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 3-7 memory and registers 3 (1) mc68hc705l28 only timer counter high (tch) $0028 1111 1111 timer counter low (tcl) $0029 1111 1100 alternate counter high (ach) $002a 1111 1111 alternate counter low (acl) $002b 1111 0011 timer control 1 (tcr1) $002c ic1ie ic2ie oc1ie toie co1e iedg1 iedg2 olv1 0000 0uu0 timer control 2 (tcr2) $002d oc2ie co2e olv2 0000 0000 timer status (tsr) $002e ic1f ic2f oc1f tof tcap1 tcap2 oc2f uuuu 11u0 reserved $002f port d data (portd) $0030 unaffected port d data direction (ddrd) $0031 ddrd5 ddrd4 ddrd3 ddrdd2 ddr1 ddrd0 ??00 0000 port d control (cond) $0032 cond5 cond4 cond3 cond2 cond1 cond0 ??00 0000 port d select (seld) $0033 pd5/ scl0 pd4/ sda0 pd3/ tcmp2 pd2/ tcap2 pd1/ tcmp1 pd0/ tcap1 ??00 0000 reserved $34C$3f table 3-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 3-8 MC68HC05L28 memory and registers 3 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 4-1 input/output ports 4 4 input/output ports in single chip mode , the MC68HC05L28 has a total of 22 i/o lines , arranged as two 8-bit ports (a and b) and one 6-bit por t (d). each i/o line is individually prog rammab le as either input or output, under the softw are control of the data direction registers . por t d shares v ar ious i/o con?gur ations with the timer and i 2 c subsystems. t o a v oid glitches on the output pins , data should be wr itten to the i/o por t data register bef ore writing ones to the corresponding data direction register bits to set the pins to output mode. 4.1 input/output programming the bidirectional port lines may be programmed as inputs or outputs under software control. the direction of each pin is normally determined by the state of the corresponding bit in the port data direction register (ddr). each por t has an associated ddr. an y standard i/o por t pin is con?gured as an output if its corresponding ddr bit is set to a logic one . a pin is con?gured as an input if its corresponding ddr bit is cleared. at power-on or reset, all ddrs are cleared, con?guring all port pins as inputs. the data direction registers can be wr itten to or read b y the mcu . dur ing the prog r ammed output state , a read of the data register actually reads the v alue of the output data latch and not the i/o pin. the oper ation of the standard port hardware is shown schematically in figure 4-1. this is summarized in table 4-1, which shows the eff ect of reading from or wr iting to an i/o pin in various circumstances . note that the read/wr ite signal sho wn is inter nal and not a vailab le to the user. table 4-1 i/o pin states r/w ddrn action of mcu write to/read of data bit 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch, and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 4-2 MC68HC05L28 input/output ports 4 4.2 ports a and b these por ts are standard m68hc05 bidirectional i/o por ts, each compr ising a data register and a data direction register. reset does not aff ect the state of the data register , but clears the data direction register, thereby returning all port pins to input mode. writing a 1 to an y ddr bit sets the corresponding por t pin to output mode. 4.3 port d por t d is a 6-bit non-standard por t which shares its pins with the timer and i 2 c subsystems. there are f our read/wr ite registers associated with the por t f or de?ning the diff erent functions . all the por t d pins can be con?gured as input/output pins or can be used b y other subsystems within the mcu . setting bits 5-0 in the por t d select register to logical 1 con?gures the pin as dedicated to the timer or i 2 c subsystems . f or details of the alter nativ e function of each por t d pin see section 2.2.8. figure 4-1 standard i/o port structure latched data register bit ddrn data input buffer output buffer o/p data buffer m68hc05 internal connections ddrn data i/o pin 1 0 0 1 1 1 0 0 tristate 0 1 tristate i/o pin output ? input ? data direction register bit tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 4-3 input/output ports 4 4.4 port registers the f ollo wing sections e xplain in detail the individual bits in the data and control registers associated with the ports. 4.4.1 port data registers (porta, portb and portd) each bit can be con?gured as input or output via the corresponding data direction bit in the por t data direction register (ddrx). reset does not affect the state of the port data registers. each of the por t d bits is shared with another mcu subsystem. the con?gur ation of this register is determined by the setting of individual bits in the port d control register. see section 4.4.3. 4.4.2 data direction registers (ddra, ddrb and ddrd) writing a 1 to an y bit con?gures the corresponding por t pin as an output; con versely, writing any bit to 0 con?gures the corresponding port pin as an input. reset clears these registers, thus con?guring all ports as inputs. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unaffected port b data (portb) $0001 unaffected port d data (portd) $0030 unaffected address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port d data direction (ddrd) $0031 0000 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 4-4 MC68HC05L28 input/output ports 4 4.4.3 port d control register (cond) the select register , data direction register and control register deter mine the function of the i/o port, as shown in table 4-2. 4.4.4 port d select register (seld) setting bits 5-0 in the port d select register to logical 1 con?gures the pin to be dedicated to the timer or the i 2 c bus subsystems. this select bit overrides the effect that the ddr register has on the por t direction. the user m ust ensure that the ddr and cond register bits are prog rammed correctly to obtain the desired pin con?guration. pd5/scl0 port d pin 5/scl0 select 1 (set) C this pin is con?gured as the i 2 c clock and is always an open-drain i/o. if a pull-up is required then bit 5 in the ddrd and cond registers must be cleared. 0 (clear) C this pin is con?gured as i/o pin pd5. pd4/sda0 port d pin 4/scl1 select 1 (set) C this pin is con?gured as the i 2 c data pin and is alw a ys an open-dr ain i/o. if a pull-up is required then bit 4 in the ddrd and cond registers must be cleared. 0 (clear) C this pin is con?gured as i/o pin pd4. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port d control (cond) $0032 0000 0000 table 4-2 i/o con?guration functions ddrd cond function 0 0 input with pull-up 0 1 input without pull-up 1 0 push-pull output 1 1 open-drain output without pull-up address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port d select (seld) $0033 pd5/ scl0 pd4/ sda0 pd3/ tcmp2 pd2/ tcap2 pd1/ tcmp1 pd0/ tcap1 0000 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 4-5 input/output ports 4 pd3/tcmp2 port d pin 3/tcmp2 select 1 (set) C this pin is con?gured as timer output compare 2 output. setting bit 3 in the cond register makes it an open drain output 0 (clear) C this pin is con?gured as i/o pin pd3. pd2/tcap2 port d pin 2/tcap2 select 1 (set) C this pin is con?gured as timer input capture 2 input. clear ing bit 2 in the cond register enables the pull-up resistor. 0 (clear) C this pin is con?gured as i/o pin pd2. pd1/tcmp1 port d pin 1/tcmp1 select 1 (set) C this pin is con?gured as timer output compare 1 output. setting bit 1 in the cond register makes it an open drain output 0 (clear) C this pin is con?gured as i/o pin pd1. pd0/tcap1 port d pin 0/tcap1 select 1 (set) C this pin is con?gured as timer input capture 1 input. clear ing bit 0 in the cond register enables the pull-up resistor. 0 (clear) C this pin is con?gured as i/o pin pd0. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 4-6 MC68HC05L28 input/output ports 4 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 5-1 core timer 5 5 core timer the MC68HC05L28 has a 15-stage r ipple counter called the core timer (ctimer). f eatures of this timer are: timer over?ow, power-on reset (por), real time interrupt (rti) with four selectable interrupt rates, and a computer operating properly (cop) watchdog timer. figure 5-1 core timer block diagram ctof rtif ctofe rtie 0 0 rt1 rt0 cop watchdog timer (? 8) to reset logic over?ow detect circuit (? 4) to interrupt logic interrupt circuit rti select circuit $09 ctcr (core timer counter) $08 ctcsr (core timer control & status) cop clear internal processor clock 7-bit counter f op f op / 2 2 f op / 2 10 f op / 2 14 f op / 2 17 internal bus 8 8 8 por tcbp tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 5-2 MC68HC05L28 core timer 5 as sho wn in figure 5-1, the timer is dr iven b y the inter nal bus cloc k divided b y f our with a ?x ed prescaler . this signal dr iv es an 8-bit r ipple counter . the v alue of this 8-bit r ipple counter can be read by the cpu at any time, b y accessing the ctimer counter register (ctcr) at address $09. a timer o ver?o w function is implemented on the last stage of this counter , giving a possib le interr upt at the r ate of f op /1 024. the por signal (t porl ) is also der iv ed from this register , at f op /4 064. the counter register circuit is f ollow ed b y tw o more stages , with the resulting cloc k (f op /16384) dr iving the real time interr upt circuit. the r ti circuit consists of three divider stages with a 1-of-4 selector . the output of the r ti circuit is fur ther divided b y eight to dr iv e the cop w atchdog timer circuit. the r ti r ate selector bits and the r ti and ctof enab le bits and ?ags are located in the ctimer control and status register (ctcsr) at location $08. ct of (core timer o ver?o w ?ag) is a clear able , read-only status bit set when the 8-bit r ipple counter rolls ov er from $ff to $00. a cpu interr upt request will be gener ated if ct ofe is set. ct of is cleared by writing a 0 to it. writing a 1 has no effect. reset clears this bit. when ct ofe (core timer o ver?ow ?ag enab le) is set, a cpu interr upt request is gener ated when the ctof bit is set. reset clears ctofe. the core timer counter register (ctcr) is a read-only register that contains the current v alue of the 8-bit r ipple counter at the beginning of the timer chain. this counter is cloc k ed at f op /4 and can be used f or v ar ious functions including a softw are input capture . extended time per iods can be attained using the ct of function to increment a tempor ar y ram stor age location sim ulating a 16-bit (or more) counter. the pow er-on cycle clears the entire counter chain and begins cloc king the counter . after t porl cycles , the po w er-on reset circuit is released, which again clears the counter chain and allo ws the de vice to come out of reset. at this point, if reset is not asser ted, the timer star ts counting up from z ero and nor mal de vice oper ation begins . when reset is asser ted at an y time dur ing operation (other than por), the counter chain is cleared. see section 5.3 for register details. 5.1 real time interrupts (rti) the real time interr upt circuit consists of a three stage divider and a 1-of-4 selector . the cloc k frequency that drives the r ti circuit is f op /2 13 (or f op /8192), with three additional divider stages , giving a maximum interrupt period of 4 seconds at a crystal frequency (f op ) of 32khz. the ?ag (r tif) is a clear able , read-only status bit which is set when the output of the chosen (1-of-4 selection) stage becomes activ e . a cpu interr upt request is gener ated if r tie is set. r tif is cleared by wr iting a 0 to it. wr iting a 1 has no eff ect. reset clears this bit. see section 5.3 for register details. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 5-3 core timer 5 5.2 computer operating properly (cop) watchdog timer the cop w atchdog timer is implemented b y dividing the output of the r ti circuit b y eight, as sho wn in figure 5-1. the minim um cop timeout per iod is se v en times the r ti per iod. this is because the cop will be cleared asynchronously with respect to the v alue in the core timer counter register/rti divider , hence the actual cop timeout per iod will v ary betw een 7x and 8x the rti period. see table 5-1. the cop function is enab led by progr amming the copon bit in the option register (opt). see section 1.2.1. if the cop circuit times out, an inter nal reset is generated and the normal reset vector is fetched. wr iting a 0 to bit 0 of address $0ff0 pre v ents a cop timeout. when the cop is cleared, only the ?nal divide-by-eight stage is cleared (see figure 5-1). see section 5.3 for register details. 5.3 core timer registers 5.3.1 core timer control and status register (ctcsr) ctof core timer over?ow 1 (set) C the core timer has over?owed. 0 (clear) C the core timer has not over?owed. this bit is set when the core timer counter register rolls o v er from $ff to $00; an interr upt request will be generated if ctofe is set. when set, the bit may be cleared by writing a 0 to it. table 5-1 minimum cop reset times minimum cop reset at bus frequency: rt1, rt0 16.384 khz 4.194 mhz f op 00 7 s 53.2 ms 7 x (rti rate) 01 17s 105.7 ms 7 x (rti rate) 10 28s 765.8 ms 7 x (rti rate) 11 56 s 422.8 ms 7 x (rti rate) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset core timer control/status (ctcsr) $0008 ctof rtif ctofe rtie 0 0 rt1 rt0 0000 0011 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 5-4 MC68HC05L28 core timer 5 rtif real time interrupt ?ag 1 (set) C a real time interrupt has occurred. 0 (clear) C no real time interrupt has been generated. this bit is set when the output of the chosen stage becomes activ e; an interr upt request will be generated if rtie is set. when set, the bit may be cleared by writing a 0 to it. ctofe core timer over?ow enable 1 (set) C core timer over?ow interrupt is enabled. 0 (clear) C core timer over?ow interrupt is disabled. setting this bit enab les the core timer o ver?o w interr upt. a cpu interr upt request is gener ated when the ctof bit is set. clearing this bit disables the core timer over?ow interrupt capability. rtie real time interrupt enable 1 (set) C real time interrupt is enabled. 0 (clear) C real time interrupt is disabled. setting this bit enab les the real time interr upt. a cpu interr upt request is gener ated when the r tif bit is set. clearing this bit disables the real time interrupt capability. rt1, rt0 real time interrupt rate select these tw o bits select one of f our taps from the real time interr upt circuitry . reset sets both r t0 and r t1 to one , selecting the lo w est per iodic r ate and theref ore the maxim um time in which to alter them if necessary. the cop reset times are also determined by these two bits. care should be taken when altering rt0 and r t1 if a timeout is imminent or the timeout per iod is uncertain. if the selected tap is modi?ed dur ing a cycle in which the counter is s witching, an r tif could be missed or an additional one could be gener ated. to avoid problems , the cop should be cleared before changing the rti taps. seetable 5-2 for some example rti periods. table 5-2 example rti periods bus frequency f op = 2 mhz rt1 rt0 division ratio rti period minimum cop period 0 0 2 14 8.2ms 57.3ms 0 1 2 15 16.4ms 114.7ms 1 0 2 16 32.8ms 229.4ms 1 1 2 17 65.5ms 458.8ms tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 5-5 core timer 5 5.3.2 core timer counter register (ctcr) the core timer counter register is a read-only register , which contains the current v alue of the 8-bit ripple counter at the beginning of the timer chain. reset clears this register. 5.4 core timer during wait the cpu cloc k halts dur ing the w ait mode, b ut the core timer remains activ e . if the interr upts are enabled, then a ctimer interrupt will cause the processor to exit the wait mode. 5.5 core timer during stop the timer is cleared when going into st op mode. when stop is exited by an external interrupt or an e xter nal reset, the inter nal oscillator will restar t, f ollow ed b y an inter nal processor stabilization delay (t porl ). the timer is then cleared and operation resumes. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset core timer counter (ctcr) $0009 0000 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 5-6 MC68HC05L28 core timer 5 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-1 16-bit programmable timer 6 6 16-bit programmable timer the MC68HC05L28 has a 16-bit prog rammab le timer . this timer consists of a 16-bit read-only free-r unning counter , with a ?x ed divide-b y-f our prescaler , plus input capture/output compare circuitry. selected input edges cause the current counter v alue to be latched into a 16-bit input capture register so that softw are can later read this v alue to deter mine when the edge occurred. when the free r unning counter v alue matches the v alue in the output compare registers , the prog rammed pin action takes place. see figure 6-1 for a block diagram of the timer. as the timer has a 16-bit architecture, each segment is represented by two 8-bit registers. these registers contain the high and lo w b yte of that functional segment. accessing the lo w b yte of a speci?c timer function allo ws full control of that function, while accessing the high b yte inhibits that speci?c timer function until the low byte is also accessed. note: the i-bit in the ccr should be set, while manipulating both the high and lo w b yte register of a speci?c timer function, to ensure that an interrupt does not occur. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-2 MC68HC05L28 16-bit programmable timer 6 figure 6-1 16-bit programmable timer block diagram internal internal bus 8 output compare register 1 processor clock 8-bit buffer 4 high low 16-bit free-running counter counter alternate register register 1 register 2 input capture internal timer bus over?ow detect circuit edge detect tcap1 tcmp2 tcmp1 d clk q compare output register 2 input capture byte byte high byte low byte high byte low byte high byte low byte low byte high byte circuit 1 compare output circuit 2 compare output circuit 1 edge detect circuit 2 tcap2 pin pin pin pin d clk q $28 $29 $2a $2b $24 $22 $23 $20 $21 $26 $27 $25 ic1f ic2f oc1f tof ocf2 ic1ie ic2ie oc1ie toie iedg1 iedg2 olvl1 interrupt circuit oc2ie olvl2 tsr ($2e) tcr1 ($2c) tcr2 ($2d) c c reset interrupt routine tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-3 16-bit programmable timer 6 6.1 counter the ke y element in the prog rammab le timer is a 16-bit, free-r unning counter, or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2s if the inter nal bus cloc k is 2 mhz. the counter is incremented dur ing the low por tion of the inter nal bus clock. softw are can read the counter at an y time without aff ecting its value. 6.1.1 counter high register counter low register alternate counter high register alternate counter low register the doub le-byte , free-r unning counter can be read from either of tw o locations: the counter register at $28-$29 or the alter nate counter register at $2a-$2b . a read from only the less signi?cant b yte (lsb) of the free-r unning counter , $29 or $2b , receiv es the count v alue at the time of the read. if a read of the free-r unning counter or alter nate counter register ?rst addresses the more signi?cant b yte (msb), $28 or $2a, the lsb is tr ansf erred to a b uffer . this b uffer v alue remains ?x ed after the ?rst msb read, e v en if the user reads the msb se ver al times . this b uff er is accessed when reading the free-r unning counter or alter nate counter register lsb and thus completes a read sequence of the total counter v alue . in reading either the free-r unning counter or alter nate counter register , if the msb is read, the lsb m ust also be read to complete the sequence . the alter nate counter register diff ers from the counter register only in that a read of the msb does not clear t of . theref ore the counter alter nate register can be read at an y time without the possibility of missing timer over?ow interrupts due to clearing of tof. if the timer o ver?o w ?ag (t of) is set when the counter register lsb is read, then a read of the tsr will clear the ?ag. the free-r unning counter is set to $fffc dur ing reset and is alw ays a read-only register. during a po w er-on reset, the counter is also preset to $fffc and begins r unning after the oscillator star t-up dela y . because the free-r unning counter is 16 bits preceded b y a ?x ed divide- by-four prescaler , the v alue in the free-r unning counter repeats e very 262 144 internal bus clock cycles. t of is set when the counter o ver?o ws (from $ffff to $0000); this will cause an interr upt if toie is set. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer counter high (tch) $0028 (bit 15) (bit 8) $ff timer counter low (tcl) $0029 $fc alternate counter high (ach) $002a (bit 15) (bit 8) $ff alternate counter low (acl) $002b $fc tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-4 MC68HC05L28 16-bit programmable timer 6 bits 8C15 msb of counter/alternate counter register a read of only the more signi?cant b yte (msb) transf ers the lsb to a b uffer, which remains ?xed after the ?rst msb read, until the lsb is also read. bits 0C7 lsb of counter/alternate counter register a read of only the less signi?cant byte (lsb) receives the count value at the time of reading. 6.2 timer functions the 16-bit prog rammab le timer is monitored and controlled b y a g roup of ?fteen registers , full details of which are contained in the f ollowing paragraphs . an e xplanation of the timer functions is also given. 6.2.1 timer control registers the timer control registers at locations $2c and $2d are read/wr ite registers . fiv e bits control interr upts associated with the timer status register ?ags ic1f , ic2f, oc1f , oc2f and t of. two bits control which edge is signi?cant to the input capture 1 and 2 edge detectors. 6.2.1.1 timer control register 1 (tcr1) ic1ie input capture 1 interrupt enable 1 (set) C input capture 1 interrupt enabled. 0 (clear) C input capture 1 interrupt disabled. ic2ie input capture 2 interrupt enable 1 (set) C input capture 2 interrupt enabled. 0 (clear) C input capture 2 interrupt disabled. oc1ie output compare 1 interrupt enable 1 (set) C output compare 1 interrupt enabled. 0 (clear) C output compare 1 interrupt disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control 1 (tcr1) $002c ic1ie ic2ie oc1ie toie co1e iedg1 iedg2 olvl1 0000 0uu0 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-5 16-bit programmable timer 6 toie timer over?ow interrupt enable 1 (set) C timer over?ow interrupt enabled. 0 (clear) C timer over?ow interrupt disabled. co1e timer compare 1 output enable 1 (set) C output of timer compare 1 is enabled. 0 (clear) C output of timer compare 1 is disabled. reset clears this bit. iedg1 input edge 1 this bit deter mines which le vel tr ansition on tcap1 pin will tr igger the tr ansf er of the free-r unning counter to input capture register. 1 (set) C tcap1 is rising edge sensitive. 0 (clear) C tcap1 is falling edge sensitive. when iedg1 is set, a r ising edge on the tcap1 pin will tr igger a tr ansf er of the free-r unning counter v alue to the input capture register . when clear , a f alling edge tr iggers the tr ansfer. reset does not affect the iedg1 bit. iedg2 input edge 2 this bit deter mines which le vel tr ansition on tcap2 pin will tr igger the tr ansf er of the free-r unning counter to input capture register 2. 1 (set) C tcap2 is rising edge sensitive. 0 (clear) C tcap2 is falling edge sensitive. when iedg2 is set, a r ising edge on the tcap2 pin will tr igger a tr ansf er of the free-r unning counter v alue to the input capture register . when clear , a f alling edge tr iggers the tr ansfer. reset does not affect the iedg2 bit. olvl1 output level 1 this bit deter mines the le v el that is cloc k ed into the output le v el register b y the ne xt successful output compare 1 and which will appear on the tcmp1 pin. 1 (set) C a high output level will appear on the tcmp1 pin. 0 (clear) C a low output level will appear on the tcmp1 pin. when ol vl1 is set, a high output le v el will be cloc k ed into the output le v el register b y the ne xt successful output compare , and will appear on the tcmp1 pin. when clear , it will be a lo w level that will appear on the tcmp1 pin. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-6 MC68HC05L28 16-bit programmable timer 6 6.2.1.2 timer control register 2 (tcr2) oc2ie output compare 2 interrupt enable 1 (set) C output compare 2 interrupt enabled. 0 (clear) C output compare 2 interrupt disabled. co2e timer compare 2 output enable 1 (set) C output of timer compare 2 is enabled. 0 (clear) C output of timer compare 2 is disabled. reset clears this bit. olvl2 output level 2 this bit deter mines the le v el that is cloc k ed into the output le v el register b y the ne xt successful output compare 2 and which will appear on the tcmp2 pin. 1 (set) C a high output level will appear on the tcmp2 pin. 0 (clear) C a low output level will appear on the tcmp2 pin. when ol vl2 is set, a high output le v el will be cloc k ed into the output le v el register b y the ne xt successful output compare , and will appear on the tcmp2 pin. when clear , it will be a lo w level that will appear on the tcmp2 pin. bits 1, 2 4, 6 and 7 unused; always read 0. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control 2 (tcr2) $002d 0 0 oc2ie 0 co2e 0 0 olvl2 0000 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-7 16-bit programmable timer 6 6.2.2 timer status register (tsr) the timer status register ($2e) contains the status bits f or the interr upt conditions icf , ocf, tof. accessing the timer status register satis?es the ?rst condition required to clear the status bits . the remaining step is to access the register corresponding to the status bit. ic1f input capture 1 ?ag 1 (set) C valid input capture has occurred. 0 (clear) C no input capture has occurred. this bit is set when the selected polar ity of edge is detected b y the input capture 1 edge detector ; an input capture interr upt will be gener ated, if ic1ie is set. ic1f is cleared b y reading the tsr and then the input capture low 1 register at $21. ic2f input capture 2 ?ag 1 (set) C valid input capture has occurred. 0 (clear) C no input capture has occurred. this bit is set when the selected polar ity of edge is detected b y the input capture 2 edge detector ; an input capture interr upt will be gener ated, if ic2ie is set. ic2f is cleared b y reading the tsr and then the input capture low 2 register at $25. oc1f output compare 1 ?ag 1 (set) C a valid output compare has occurred. 0 (clear) C no output compare has occurred. this bit is set when the output compare register contents match those of the free-r unning counter; an output compare interr upt will be gener ated, if oc1ie is set. oc1f is cleared b y reading the tsr and then the output compare low 1 register at $23. tof timer over?ow ?ag 1 (set) C timer over?ow has occurred. 0 (clear) C no timer over?ow has occurred. this bit is set when the free-r unning counter o ver?o ws from $ffff to $0000; a timer o ver?ow interrupt will occur, if toie is set. tof is cleared b y reading the tsr and the counter lo w register at $29. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status (tsr) $002e ic1f ic2f oc1f tof tcap1 tcap2 oc2f 0 uuuu 11u0 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-8 MC68HC05L28 16-bit programmable timer 6 when using the timer o ver?o w function and reading the free-r unning counter at r andom times to measure an elapsed time, a problem may occur whereby the timer over?ow ?ag is unintentionally cleared if: C the timer status register is read or written when tof is set and C the lsb of the free-running counter is read, but not for the purpose of servicing the ?ag. reading the alter nate counter register instead of the counter register will a v oid this potential problem. tcap1 timer capture 1 this bit re?ects the current status of the timer capture 1 input. note: on the MC68HC05L28, tcap1 is connected directly to pd0 which def aults to an input with pull-up on reset. tcap1 will be 1 unless pd0 is externally driven low. tcap2 timer capture 2 this bit re?ects the current state of the timer capture 2 input. note: on the MC68HC05L28, tcap2 is connected directly to pd2 which def aults to an input with pull-up on reset. tcap2 will be 1 unless pd2 is externally driven low. oc2f output compare 2 ?ag 1 (set) C a valid output compare has occurred. 0 (clear) C no output compare has occurred. this bit is set when the output compare register contents match those of the free-r unning counter; an output compare interr upt will be gener ated, if oc2ie is set. oc2f is cleared b y reading the tsr and then the output compare low 2 register at $27. bit 0 always reads zero. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-9 16-bit programmable timer 6 6.2.3 input capture registers input capture is a technique whereb y an e xter nal signal (connected to the tcap1 or tcap2 pin) is used to tr igger a read of the free-r unning counter . in this w a y it is possib le to relate the timing of an e xter nal signal to the inter nal counter v alue , and hence to elapsed time . there are tw o identical input capture registers. 6.2.3.1 input capture register 1 the tw o 8-bit registers that mak e up the 16-bit input capture register 1 are read-only , and are used to latch the value of the free-r unning counter after the corresponding input capture edge detector senses a v alid tr ansition. the le v el tr ansition that tr iggers the counter tr ansf er is de?ned b y the input edge bit (iedg1). the most signi?cant 8 bits are stored in the input capture high 1 register at $20 and the least signi?cant in the input capture low 1 register at $21. an interr upt can accompan y a capture if the corresponding interr upt enab le bit (ic1ie in timer control register 1 at $2c) is set. the result obtained from an input capture will be one g reater than the v alue of the free-r unning counter on the r ising edge of the inter nal bus cloc k preceding the e xternal transition. this delay is required for inter nal synchronisation. resolution is one count of the free-r unning counter , which is four internal bus clock cycles. the free-r unning counter contents are tr ansf erred to the input capture register on each v alid signal tr ansition whether the input capture 1 ?ag (ic1f) is set or clear . the input capture register alw ays contains the free-running counter v alue that corresponds to the most recent input capture . after a read of the input capture register msb ($20), the counter tr ansf er is inhibited until the lsb ($21) is also read. this causes the time used in the input capture softw are routine and its inter action with the main prog r am to deter mine the minim um pulse per iod. a read of the input capture register lsb ($21) does not inhibit the free-r unning counter tr ansf er since the tw o actions occur on opposite edges of the internal bus clock. reset does not aff ect the contents of the input capture register , except when exiting stop mode. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high 1 (ich1) $0020 unaffected input capture low 1 (icl1) $0021 unaffected tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-10 MC68HC05L28 16-bit programmable timer 6 6.2.3.2 input capture register 2 the tw o 8-bit registers that mak e up the 16-bit input capture register 2 are read-only , and are used to latch the value of the free-r unning counter after the corresponding input capture edge detector senses a v alid tr ansition. the le v el tr ansition that tr iggers the counter tr ansf er is de?ned b y the input edge bit (iedg2). the most signi?cant 8 bits are stored in the input capture high 2 register at $24 and the least signi?cant in the input capture low 2 register at $25. an interr upt can accompan y a capture if the corresponding interr upt enab le bit (ic2ie in timer control register 1 at $2c) is set. the result obtained from an input capture will be one g reater than the v alue of the free-r unning counter on the r ising edge of the inter nal bus cloc k preceding the e xternal transition. this delay is required for inter nal synchronisation. resolution is one count of the free-r unning counter , which is four internal bus clock cycles. the free-r unning counter contents are tr ansf erred to the input capture register on each v alid signal tr ansition whether the input capture 2 ?ag (ic2f) is set or clear . the input capture register alw ays contains the free-running counter v alue that corresponds to the most recent input capture . after a read of the input capture register msb ($24), the counter tr ansf er is inhibited until the lsb ($25) is also read. this causes the time used in the input capture softw are routine and its inter action with the main prog r am to deter mine the minim um pulse per iod. a read of the input capture register lsb ($25) does not inhibit the free-r unning counter tr ansf er since the tw o actions occur on opposite edges of the internal bus clock. reset does not aff ect the contents of the input capture register , e xcept when e xiting stop mode. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high 2 (ich2) $0024 unaffected input capture low 2 (icl2) $0025 unaffected tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-11 16-bit programmable timer 6 6.2.4 output compare registers output compare is a technique that may be used, for example, to generate an output waveform, or to signal when a speci?c time per iod has elapsed, b y presetting the output compare register to the appropriate value . there are tw o output compare registers C oc1 and oc2. all the bits are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. 6.2.4.1 output compare register 1 the 16-bit output compare register 1 is made up of tw o 8-bit registers at locations $22 (msb) and $23 (lsb). the contents of the output compare 1 register are compared with the contents of the free-r unning counter once e ver y f our inter nal processor cloc k cycles . if a match is f ound, the output compare 1 ?ag (oc1f) in the timer status register is set and the output le vel 1 (olvl1) bit is cloc k ed to the tcmp1 pin. the output compare 1 register v alues and the output le v el 1 bit should be changed after each successful compar ison to estab lish a ne w elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oc1ie) is set. after a processor wr ite cycle to the output compare register 1 containing the msb ($22), the output compare function is inhibited until the lsb ($23) is also wr itten. the user m ust wr ite both b ytes (locations) if the msb is wr itten ?rst. a wr ite made only to the lsb will not inhibit the compare function. the processor can wr ite to either b yte of the output compare register 1 without aff ecting the other byte . the output le v el 1 bit (ol vl1) is cloc k ed to the output le v el 1 register whether the output compare 1 ?ag (oc1f) is set or clear . the minim um time required to update the output compare 1 register is a function of the prog r am r ather than the inter nal hardw are . because the output compare 1 ?ag and the output compare 1 register are not de?ned at po w er on, and not aff ected b y reset, care m ust be tak en when initialising output compare functions with softw are . the following procedure is recommended: 1) write to output compare high 1 to inhibit further compares; 2) read the timer status register to clear oc1f (if set); 3) write to output compare low 1 to enable the output compare 1 function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high 1 (och1) $0022 unaffected output compare low 1 (ocl1) $0023 unaffected tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-12 MC68HC05L28 16-bit programmable timer 6 6.2.4.2 output compare register 2 the 16-bit output compare register 2 is made up of tw o 8-bit registers at locations $26 (msb) and $27 (lsb). the contents of the output compare 2 register are compared with the contents of the free-r unning counter once e ver y f our inter nal processor cloc k cycles . if a match is f ound, the output compare 2 ?ag (oc2f) in the timer status register is set and the output le vel 2 (olvl2) bit is cloc k ed to the tcmp2 pin. the output compare 2 register v alues and the output le v el 2 bit should be changed after each successful compar ison to estab lish a ne w elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oc2ie) is set. after a processor wr ite cycle to the output compare register 1 containing the msb ($26), the output compare function is inhibited until the lsb ($27) is also wr itten. the user m ust wr ite both b ytes (locations) if the msb is wr itten ?rst. a wr ite made only to the lsb will not inhibit the compare function. the processor can wr ite to either b yte of the output compare 2 register without aff ecting the other byte . the output le v el 2 bit (ol vl2) is cloc k ed to the output le v el 2 register whether the output compare 2 ?ag (oc2f) is set or clear . the minim um time required to update the output compare 2 register is a function of the prog r am r ather than the inter nal hardw are . because the output compare 2 ?ag and the output compare 2 register are not de?ned at po w er on, and not aff ected b y reset, care m ust be tak en when initialising output compare functions with softw are . the following procedure is recommended: C write to output compare high 2 to inhibit further compares; C read the timer status register to clear oc2f (if set); C write to output compare low 2 to enable the output compare 2 function. note: as the tcmp1 and tcmp2 pins are shared with por t d , output compares 1 and 2 cannot be used f or compare when the pins are selected to be input. ho wever, the data register can still be used as a temporary store. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high 2 (och2) $0026 unaffected output compare low 2 (ocl2) $0027 unaffected tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-13 16-bit programmable timer 6 6.3 timer during wait mode in wait mode all cpu action is suspended, whereas the timer continues to run. 6.4 timer during stop mode in the stop mode all mcu clocks are stopped, so the timer stops counting. if stop is exited by an interrupt the counter retains the last count value. if the device is reset, the counter is forced to $fffc. during stop , if at least one v alid input capture edge occurs at the tcap pins , the input capture detect circuit is ar med. this does not set an y timer ?ags nor w ak e up the mcu . when the mcu does w ak e up , ho wever , there is an activ e input capture ?ag and data from the ?rst v alid edge that occurred during the stop period. if the device is reset to exit stop mode, no input capture ?ag or data remains, even if a valid input capture edge occurred. 6.5 timer state diagrams the relationships betw een the inter nal clock signals , the counter contents and the status of the ?ag bits are shown in the following diagrams . it should be noted that the signals labelled inter nal (processor clock, timer clocks and reset) are not available to the user. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-14 MC68HC05L28 16-bit programmable timer 6 figure 6-2 timer state timing diagram for reset figure 6-3 timer state timing diagram for input capture internal processor clock internal reset 16-bit counter external reset or end of por internal timer clocks ? ? ? $fffc $fffd $fffe $ffff note: the counter and timer control registers are the only ones affected by power-on or external reset. t00 t01 t11 t10 internal processor clock 16-bit counter $f123 $f124 $f125 $f126 internal timer clocks ? ? ? t00 t01 t11 t10 internal capture latch $f124 $???? input capture register input capture ?ag input edge } } } } note: if the input edge occurs in the shaded area from one timer state t10 to the ne xt timer state t10, then the input capture ?ag will be set during the next t11 state. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 6-15 16-bit programmable timer 6 figure 6-4 timer state timing diagram for output compare figure 6-5 timer state timing diagram for timer over?ow internal processor clock 16-bit counter $f456 $f457 $f458 $f459 internal timer clocks ? ? ? t00 t01 t11 t10 $f457 cpu writes $f457 output compare ?ag and tcmp note: (1) the cpu wr ite to the compare registers ma y tak e place at an y time, b ut a compare only occurs at timer state t01. thus a four cycle difference may exist between the write to the compare register and the actual compare. (2) the output compare ?ag is set at the timer state t11 that f ollo ws the compar ison match ($f457 in this example). output compare register compare register latch (note 2) (note 1) (note 1) internal processor clock 16-bit counter $ffff $0000 $0001 $0002 internal timer clocks ? ? ? t00 t01 t11 t10 note: the timer o ver?o w ?ag is set at timer state t11 (tr ansition of counter from $ffff to $0000). it is cleared b y a read of the timer status register dur ing the internal processor clock high time, followed by a read of the counter low register. timer over?ow ?ag tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6-16 MC68HC05L28 16-bit programmable timer 6 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 7-1 liquid crystal display driver module 7 7 liq uid cr yst al displa y driver module this chapter descr ibes the gener ic m68hc05 f amily lcd dr iv er module . an y diff erences in the module speci?c to the MC68HC05L28 are indicated along with the generic description. the m68hc05 family lcd driv er module can be con?gured with up to 24 frontplane dr ivers and a maximum of 4 backplane drivers. this allows a maximum of 96 lcd segments. the lcd dr iv er module on the MC68HC05L28 suppor ts 18 frontplanes and 4 bac kplanes, allowing a maxim um of 72 lcd segments . each segment is controlled b y a corresponding bit in the lcd ram. the mode of oper ation is determined by the v alues set in the lcd control register at $1e. at reset or on po wer-up , the dr iv ers are con?gured in the def ault duple x mode , 1/2 bias with 2 backplanes and 18 frontplanes. also at power-up or reset the on/off control for the display, the dison bit in the lcd control (lcd) register , is cleared disab ling the lcd dr ivers . figure 7-1 shows a block diagram of the lcd system. figure 7-1 lcd system block diagram 8 13 lcd ram segment driver internal data bus internal address bus control logic backplane driver voltage generator v lcd bp0 bp1 bp2 bp3 fp0 fp17 internal signals tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 7-2 MC68HC05L28 liquid crystal display driver module 7 7.1 lcd ram data to be displayed on the lcd must be wr itten into the lcd ram. the lcd ram is compr ised of 12 b ytes of ram (in the MC68HC05L28 s memor y map) at $0040 C $004b . the 96 bits in the lcd ram correspond to the 96 segments that can be dr iven by the frontplane/backplane drivers. table 7-1 shows how the lcd ram is organized. writing a 1 to a given location will result in the corresponding displa y segment being activ ated when the dison bit is set. the lcd ram is a dual por t ram that interf aces with the inter nal address and data b uses of the mcu . it is possib le to read from lcd ram locations f or scrolling pur poses . when dison = 0, the lcd ram can be used as main on-chip ram. 7.2 lcd operation the lcd driv er module can oper ate in four modes providing different multiplex ratios and number of backplanes as follows: ? 1/2 bias, 2 backplanes ? 1/3 bias, 2 backplanes ? 1/3 bias, 3 backplanes ? 1/4 bias, 4 backplanes table 7-1 lcd ram organization lcd ram data address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $40 fp1-bp3 fp1-bp2 fp1-bp1 fp1-bp0 fp0-bp3 fp0-bp2 fp0-bp1 fp0-bp0 $41 fp3-bp3 fp3-bp2 fp3-bp1 fp3-bp0 fp2-bp3 fp2-bp2 fp2-bp1 fp2-bp0 $42 fp5-bp3 fp5-bp2 fp5-bp1 fp5-bp0 fp4-bp3 fp4-bp2 fp4-bp1 fp4-bp0 $43 fp7-bp3 fp7-bp2 fp7-bp1 fp7-bp0 fp6-bp3 fp6-bp2 fp6-bp1 fp6-bp0 $44 fp9-bp3 fp9-bp2 fp9-bp1 fp9-bp0 fp8-bp3 fp8-bp2 fp8-bp1 fp8-bp0 $45 fp11-bp3 fp11-bp2 fp11-bp1 fp11-bp0 fp10-bp3 fp10-bp2 fp10-bp1 fp10-bp0 $46 fp13-bp3 fp13-bp2 fp13-bp1 fp13-bp0 fp12-bp3 fp12-bp2 fp12-bp1 fp12-bp0 $47 fp15-bp3 fp15-bp2 fp15-bp1 fp15-bp0 fp14-bp3 fp14-bp2 fp14-bp1 fp14-bp0 $48 fp17-bp3 fp17-bp2 fp17-bp1 fp17-bp0 fp16-bp3 fp16-bp2 fp16-bp1 fp16-bp0 $49 fp19-bp3 fp19-bp2 fp19-bp1 fp19-bp0 fp18-bp3 fp18-bp2 fp18-bp1 fp18-bp0 $4a fp21-bp3 fp21-bp2 fp21-bp1 fp21-bp0 fp20-bp3 fp20-bp2 fp20-bp1 fp20-bp0 $4b fp23-bp3 fp23-bp2 fp23-bp1 fp23-bp0 fp22-bp3 fp122-bp2 fp22-bp1 fp22-bp0 these lcd pins are not available on the MC68HC05L28/ mc68hc705l28. the corresponding ram bytes ($49 to $4b) can continue to be used as main on-chip ram. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 7-3 liquid crystal display driver module 7 the oper ating mode is selected at po w er on using the m ultiplex r atio bits (mux3 and mux4) in the lcd control register as shown in table 7-2. it is recommended that the dison bit in the lcd register is not set ( display is disabled) until the multiple x r ate is selected. the v oltage le v els required f or the diff erent m ultiple x r ates are gener ated internally by a resistive divider chain between v lcd , v dd and v ss . the 2-way multiple x with 1/3 bias and the three and f our-way multiple x options require f our voltage levels , whereas the tw o-way multiple x with 1/2 bias needs only three le vels . resistors r1, r2 and r3 are v alued at 25k? 40%. figure 7-2 sho ws the resistiv e divider chain netw or k that is used to produce the various lcd waveforms outlined in section 7.3. note: v lcd may not exceed the positive power supply voltage v dd . note: the v lcd option is not a vailab le on the MC68HC05L28 or mc68hc705l28, b ut is included here f or completeness of the gener ic module descr iption. bit 6 of the lcd control register must be cleared. 7.3 timing signals and lcd voltage waveforms the lcd timing signals are all der iv ed from the main system cloc k; with a b us frequency of 2 mhz (f osc = 4 mhz) the fr ame r ate will be 61 hz f or 2 and 4-w a y m ultiple xing and 91 hz f or 3-w ay multiple xing (see t able 7-2). an e xtr a divide-b y-tw o stage can be included in the lcd cloc k generator b y setting fdisp in the lcd register . this will result in the fr ame rate being halved. for figure 7-2 voltage level selection v lcd v dd bit 0, $1e bit 6, $1e v ss r3 r2 r1 2 bp, 1/2 bias v2 v1 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 7-4 MC68HC05L28 liquid crystal display driver module 7 example , when 3-w a y m ultiple xing is used, a fr ame r ate of 45.5 hz instead of 91 hz can be obtained. see section 7.4. figure 7-3 to figure 7-6 sho w the bac kplane w avefor ms and some e xamples of frontplane waveforms for each of the operating modes. the bac kplane w avefor ms are contin uous and repetitiv e (e ver y 2 fr ames); the y are ?x ed within each operating mode and are not affected by the data in the lcd ram. the frontplane w avefor ms are dependent on the lcd segments to be dr iv en as de?ned in the lcd ram. each on segment m ust ha v e a diff erential dr iving v oltage (bp-fp) applied to it once in each fr ame; the lcd dr iv er module hardw are uses the data in the lcd ram to constr uct the frontplane waveform to meet this criterion. figure 7-3 lcd waveform with 2 backplanes, 1/2 bias v0 v2 v dd /v lcd v dd /v lcd v2 v0 v dd /v lcd v2 v0 v dd /v lcd v2 v0 v dd /v lcd v2 v0 v dd /v lcd v2 v0 bp0 bp1 fpx, example 1 fpx, example 2 fpx, example 3 fpx, example 4 on off 1 frame note: in this mode v1=v2 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 7-5 liquid crystal display driver module 7 figure 7-4 lcd waveform with 2 backplanes, 1/3 bias v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 v2 v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 bp0 bp1 fpx, example 1 fpx, example 2 fpx, example 3 fpx, example 4 on off 1 frame v1 v dd /v lcd v2 v1 v0 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 7-6 MC68HC05L28 liquid crystal display driver module 7 figure 7-5 lcd waveform with 3 backplanes v dd /v lcd v2 v1 v0 bp0 bp1 v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 bp2 v dd /v lcd v2 v1 v0 fpx, example 1 v dd /v lcd v2 v1 v0 fpx, example 2 v dd /v lcd v2 v1 v0 fpx, example 3 on off 1 frame tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 7-7 liquid crystal display driver module 7 figure 7-6 lcd waveform with 4 backplanes v dd /v lcd v2 v1 v0 1 frame v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 v dd /v lcd v2 v1 v0 bp0 bp1 bp2 bp3 fpx, example 1 fpx, example 2 fpx, example 3 on off tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 7-8 MC68HC05L28 liquid crystal display driver module 7 7.4 lcd control register vlcdon lcd voltage select the v lcd option is not a vailab le on the MC68HC05L28 or mc68hc705l28, theref ore , this bit must be cleared. fdisp display frequency 1 (set) C an extra divide by two stage is included in the lcd clock generator to giv e a reduced fr ame rate. for example , in the 3-w ay multiplexing mode, a frame rate of 45.5 hz instead of 91 hz can be achieved. 0 (clear) C default frame rate is used. mux4, mux3 multiplex ratio these two bits select the multiplex ratio to be 2, 3 or 4 backplanes. dison display on/off 1 (set) C display is on. 0 (clear) C display is off reserved bits bits 4, 5 and 7 are reserved for future use and must be set to 0 when writing to this register. 7.5 lcd during wait mode the lcd does not function during wait mode. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset lcd control register (lcd) $001e vlcdon fdisp mux4 mux3 dison ?000 0000 table 7-2 multiplex ratio/backplane selection mux4 mux3 backplanes bias frequency 0 0 2 1/2 61 hz 0 1 3 1/3 91 hz 1 0 4 1/3 61 hz 1 1 2 1/3 61 hz tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-1 i 2 c-bus 8 8 i 2 c-bus i 2 c-b us is a tw o-wire , bidirectional ser ial b us that pro vides a simple , ef?cient w a y to e xchange data between devices . being a tw o-wire device , the i 2 c-bus minimiz es the need f or large n umbers of connections between devices, and eliminates the need for an address decoder. the b us is suitab le f or applications in v olving frequent comm unications betw een a n umber of devices over short distances. the number of de vices connected to the i 2 c-b us is limited only b y a maximum bus capacitance of 400pf; it has a maximum data rate of 100 kbits per second. the i 2 c-b us system is a tr ue m ulti-master b us including collision detection and arbitr ation to prev ent data corr uption if tw o or more masters attempt to control the b us sim ultaneously . this feature pro vides the capability f or comple x applications with m ultiprocessor control. it ma y also be used for r apid testing and alignment of end products via e xter nal connections to an assemb ly line computer. the i 2 c-bus function is enabled by the men bit in the i 2 c-bus control register (mcr). 8.1 i 2 c-bus features ? multi-master operation ? software-programmable for one of 32 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost-driven interrupt with automatic switching from master to slave mode ? calling address identi?cation interrupt ? generates/detects the start or stop signal ? repeated start signal generation ? generates/recognizes the acknowledge bit ? bus busy detection tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-2 MC68HC05L28 i 2 c-bus 8 8.2 i 2 c-bus system con?guration the i 2 c-b us system uses a ser ial data line and a ser ial clock line for data transfer. all the devices connected to it must have open drain or open collector outputs. a logic and function is used on both lines with two pull-up resistors. 8.3 i 2 c-bus protocol a standard comm unication is nor mally composed of f our par ts: st ar t signal, sla v e address tr ansmission, data tr ansfer , and st op signal. these signals are descr ibed in the f ollowing sections and illustrated in figure 8-1. 8.3.1 start signal when the b us is free (no master de vice engaging the bus; scl and sd a lines at a logic high), a master may initiate communication by sending a star t signal, which is de?ned as being a high to low transition of sd a with scl high. this signal denotes the beginning of a ne w data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. 8.3.2 transmission of the slave address the ?rst b yte of data tr ansf erred after the st ar t signal is the sla v e address tr ansmitted by the master . this address is se v en bits long, f ollow ed b y a r/ w bit which tells the sla v e the desired direction of transfer of all the following bytes (until a stop or repeated start). only the slave with the calling address that matches the one transmitted by the master responds by sending back an ackno wledge bit. this is done b y pulling the sd a lo w at the ninth cloc k (see figure 8-1). tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-3 i 2 c-bus 8 figure 8-1 i 2 c bus transmission signal diagrams scl sda scl sda acknowledge bit no acknowledge acknowledge bit no acknowledge msb lsb msb lsb msb lsb msb lsb start signal stop signal repeated start signal start signal stop signal tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-4 MC68HC05L28 i 2 c-bus 8 8.3.3 data transfer once successful sla v e addressing has been achie v ed, the data tr ansf er can proceed b yte by byte, in the direction speci?ed by the r/ w bit. data can be changed only when scl is lo w and must be held stab le while scl is high. the msb is tr ansmitted ?rst. each data b yte is eight bits long, and there is one cloc k pulse on scl f or each data bit. ev ery b yte of data m ust be f ollowed b y an ac kno wledge bit, which the receiving de vice signals b y pulling sd a lo w at the ninth cloc k. therefore , one complete data b yte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, then the sda line is left high by the slave. the master can then gener ate a st op signal to abor t the data tr ansf er or a st ar t signal to commence a new calling (called a repeated start). if the master receiver does not acknowledge the slave transmitter after one byte of transmission, it means end of data to the sla ve , which then releases the sd a line so that the master can generate the stop or start signal. 8.3.4 stop signal the master can ter minate the comm unication b y gener ating a st op signal to free the b us . a stop signal is de?ned as a low to high transition of sda while scl is high (see figure 8-1). 8.3.5 repeated start signal a repeated st ar t signal gener ates a st ar t signal without ?rst gener ating a st op signal to ter minate the comm unication. this is used b y the master to comm unicate with another sla ve, or with the same slave in a different mode (transmit/receive mode), without releasing the bus. 8.3.6 arbitration procedure the i 2 c-b us is a tr ue m ulti-master system that allo ws more than one master to be connected to it. if two or more masters try to control the bus at the same time, a clock synchronization procedure deter mines the b us clock, f or which the lo w per iod is equal to the longest cloc k low per iod and the high per iod is equal to the shor test cloc k high per iod among the masters . a data arbitr ation procedure determines the relative priority of the contending masters; a master loses arbitration if it tr ansmits logic 1 while another tr ansmits logic 0. the losing masters then immediately s witch to slave receiv e mode and stop dr iving sda outputs. the tr ansition from master to sla ve mode does not gener ate a st op condition in this case . at this point, the mal bit in the i 2 c-b us status register (msr) is set by hardware to indicate loss of arbitration. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-5 i 2 c-bus 8 8.3.7 clock synchronization since wired-and logic is perf or med on the scl line , a high to lo w tr ansition on scl aff ects all the de vices connected on the b us . the de vices star t counting their lo w per iod and once a de vices cloc k has gone lo w , it holds the scl line lo w until the cloc k high state is reached. ho wever, the change of lo w to high in this de vice cloc k ma y not change the state of the scl line if another de vice cloc k is still within its lo w period. therefore, synchronized cloc k scl is held lo w b y the de vice with the longest lo w period. de vices with shor ter low per iods enter a high w ait state dur ing this time (see figure 8-2). when all de vices concerned hav e counted off their lo w per iod, the scl line is released and pulled high. there is then no diff erence between the device clocks and the state of the scl line , and all of them star t counting their high per iods . the ?rst de vice to complete its high period pulls the scl line low again. 8.3.8 handshaking the cloc k synchronization mechanism can be used as a handshak e in data tr ansfer . the sla ve de vice ma y hold scl lo w after the completion of one b yte of data tr ansf er (nine bits). in such cases , it halts the b us clock and f orces the master cloc k into a w ait state until the sla ve releases the scl line. figure 8-2 clock synchronization scl scl1 scl2 internal counter register start counting high period wait tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-6 MC68HC05L28 i 2 c-bus 8 8.4 registers 8.4.1 i 2 c-bus address register (madr) adr7 C adr1 slave address bits these bits de?ne the sla v e address of the i 2 c-bus , and are used in sla v e mode in conjunction with the maas bit in the msr register (see section 8.4.4). these bits can be read and wr itten at an y time . bit 0 reserved by motorola. 8.4.2 i 2 c-bus frequency divider register (fdr) mbc4 C mbc0 clock rate select bits these bits can be read and written at any time. these bits are used to prescale the clock for bit rate selection. due to the potential slow rise and f all times of the scl and sd a signals the b us signals are sampled at the prescaler frequency . this sampling incurs an o v erhead of six cloc ks per scl pulse . the serial bit cloc k frequency is equal to the cpu cloc k divided b y the divider sho wn in t able 8-1, plus the sampling o v erhead of six clocks per cycle. f or a 4 mhz e xternal crystal operation, the serial bit cloc k frequency of the i 2 c-bus ranges from 460 hz to 90909 khz. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset i 2 c-bus address register (madr) $0010 adr7 adr6 adr5 adr4 adr3 adr2 adr1 0000 000 u address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset i 2 c-bus frequency divider register (fdr) $0011 mbc4 mbc3 mbc2 mbc1 mbc0 uuu0 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-7 i 2 c-bus 8 8.4.3 i 2 c-bus control register (mcr) these bits can be read and written at any time. men i 2 c-bus enable 1 (set) C i 2 c-bus interf ace system is enab led. this bit m ust be set bef ore any other mcr bits can be set. 0 (clear) C i 2 c-bus interf ace system is disab led and reset. this is the po wer-on reset case . when lo w , the interf ace is held in reset, b ut registers can be accessed. if the module is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating when a subsequent start condition is detected. master mode is not aware that the bus is busy, so if a start cycle is initiated the current bus cycle ma y become corr upt. this results in either the current b us master or the i 2 c-b us losing arbitr ation, after which bus operation returns to normal. mien i 2 c-bus interrupt enable 1 (set) C i 2 c-bus interrupt is requested when mif is set. 0 (clear) C i 2 c-bus interrupt is disabled. table 8-1 i 2 c-bus prescaler mcb4-0 divider mcb4-0 divider mcb4-0 divider mcb4-0 divider 0 0 0 0 0 22 0 1 0 0 0 88 1 0 0 0 0 352 1 1 0 0 0 1408 0 0 0 0 1 24 0 1 0 0 1 96 1 0 0 0 1 384 1 1 0 0 1 1536 0 0 0 1 0 28 0 1 0 1 0 112 1 0 0 1 0 448 1 1 0 1 0 1792 0 0 0 1 1 34 0 1 0 1 1 136 1 0 0 1 1 544 1 1 0 1 1 2176 0 0 1 0 0 44 0 1 1 0 0 176 1 0 1 0 0 704 1 1 1 0 0 2816 0 0 1 0 1 48 0 1 1 0 1 192 1 0 1 0 1 768 1 1 1 0 1 3072 0 0 1 1 0 56 0 1 1 1 0 224 1 0 1 1 0 896 1 1 1 1 0 3584 0 0 1 1 1 68 0 1 1 1 1 272 1 0 1 1 1 1088 1 1 1 1 1 4352 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset i 2 c-bus control register (mcr) $0012 men mien msta mtx txak 0000 0uuu tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-8 MC68HC05L28 i 2 c-bus 8 msta master/slave mode select 1 (set) C master mode; send start signal when set. 0 (clear) C slave mode; send stop signal when cleared. this bit is cleared on reset. when mst a is changed from 0 to a 1, a st ar t signal is gener ated on the b us and the master mode is selected. when this bit changes from a 1 to a 0, a st op signal is gener ated and the sla v e mode is selected. in master mode , clear ing mst a and then immediately setting it gener ates a repeated st ar t signal without gener ating a st op signal (see figure 8-1). mtx transmit/receive mode select 1 (set) C transmit mode. 0 (clear) C receive mode. txak transmit acknowledge bit 1 (set) C no acknowledge signal response. 0 (clear) C an acknowledge signal will be sent to the bus at the ninth clock bit after receiving one byte of data. this bit only has meaning in master receive mode. bits 2C0 not implemented; always read zero. 8.4.4 i 2 c-bus status register (msr) bits in this register can be read at any time; bits 4 and 1 can be cleared at any time. mcf data transferring 1 (set) C data transmit complete. 0 (clear) C data is being transferred. maas i 2 c-bus addressed as a slave 1 (set) C i 2 c-bus is addressed as a slave. 0 (clear) C i 2 c-bus is not addressed. this bit is set when the address of the i 2 c-b us (speci?ed in madr) matches the calling address . an interr upt is gener ated pro viding the mien bit in the mcr register is set; the cpu then selects its tr ansmit/receiv e mode according to the state of the sr w bit. wr iting to the mcr register clears this bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset i 2 c-bus status register (msr) $0013 mcf maas mbb mal srw mif rxak 1000 u001 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-9 i 2 c-bus 8 mbb bus busy 1 (set) C bus is busy. 0 (clear) C bus is idle. this bit indicates the status of the b us . when a st ar t signal is detected, mbb is set. when a stop signal is detected, mbb is cleared. mal arbitration lost 1 (set) C arbitration lost. 0 (clear) C default state. mal is set b y hardw are when the arbitr ation procedure is lost dur ing a master tr ansmission mode. this bit must be cleared by software. bit 3 not implemented; always reads zero. srw read/write command 1 (set) C r/w command bit is set (read). 0 (clear) C r/w command bit is clear (write). when maas is set, the r/w command bit of the calling address sent from a master is latched into this bit. on chec king this bit, the cpu can select sla v e tr ansmit/receiv e mode according to the command of the master. mif i 2 c-bus interrupt ?ag 1 (set) C an i 2 c-bus interrupt is pending. 0 (clear) C no i 2 c-bus interrupt is pending. when this bit is set, an i 2 c-bus interrupt is generated pro vided the mien bit in the mcr register is set. mif is set when one of the following events occurs: 1) the transf er of one b yte of data is complete; mif is set at the f alling edge of the ninth clock after the byte has been received. 2) a calling address is received which matches the address of the i 2 c-bus in slave receive mode. 3) arbitration is lost. mif must be cleared by software in the interrupt routine. rxak received acknowledge bit 1 (set) C no ac kno wledge signal has been detected at the ninth cloc k after the transmission of a byte of data. 0 (clear) C an acknowledge bit has been received at the ninth clock after the transmission of a byte of data. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-10 MC68HC05L28 i 2 c-bus 8 8.4.5 i 2 c-bus data register (mdr) these bits can be read and written at any time. in master tr ansmit mode , a wr ite to this register will cause the d ata in it t o be sent to t he b us automatically , msb ?rst . i n master receiv e mode , a read of this register initiates the tr ansf er of the next incoming byte of data into the register. see figure 8-3. in slave transmit mode, the scl line is forced low until data is written into this register, to prevent transmission. similarly , in sla ve receive mode , the data b us m ust be read bef ore a tr ansmission can occur. 8.5 programming 8.5.1 initialization after a reset, the i 2 c-b us control register (mcr) is in a def ault state. bef ore the i 2 c-b us can be used, it must be initialized as follows: 1) con?gure the frequency divider register for the desired scl frequency. 2) con?gure the i 2 c-b us address register (madr) to de?ne the sla ve address of the i 2 c-bus. 3) set the men bit in the i 2 c-bus control register (mcr) to enab le the i 2 c-bus system. 4) con?gure the other bits in the mcr register. 8.5.2 start signal and the ?rst byte of data after the initialization procedure has been completed, serial data can be transmitted by selecting the master transmitter mode . if the de vice is connected to a m ulti-master b us system, the state of the i 2 c-bus busy bit (mbb) must be tested to check whether the serial bus is free. if the bus is free (mbb = 0), the st ar t condition and the ?rst b yte (the sla v e address) can be sent. an example of a program that does this is shown below: sei ;disable interrupt chflag brset 5,msr,chflag ;check the mbb bit of the status ;register. if it is set, wait address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset i 2 c-bus data register (mdr) $0014 trxd7 trxd6 trxd5 trxd4 trxd3 trxd2 trxd1 trxd0 unde?ned tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-11 i 2 c-bus 8 ;until it is clear txstart bset 4,mcr ;set transmit mode bset 5,mcr ;set master mode ;i.e. generate start condition lda calling ;get the calling address sta mdr ;transmit the calling address cli ;enable interrupt 8.5.3 software response the tr ansmission or reception of a b yte sets the data tr ansferr ing bit, mcf , which indicates that one b yte of comm unication is ?nished. also , the i 2 c-bus interr upt bit, mif , is set to gener ate an i 2 c-b us interr upt (if mien is set). figure 8-3 sho ws an e xample of a typical i 2 c-b us interr upt routine. in the interrupt routine, the ?rst step is for softw are to clear the mif bit. the mcf bit can be cleared b y reading from the i 2 c-b us data i/o register (mdr) in receiv e mode, or by writing to mdr in transmit mode. software may service the i 2 c-bus i/o in the main program by monitoring the mif bit if the interr upt function is disab led. the f ollo wing is an e xample of a softw are response by a master transmitter in the interrupt routine: isr bclr 1,msr ;clear the mif flag brclr 5,mcr,slave ;check the msta flag ;branch if slave mode brclr 4,mcr,recieve ;check the mode flag brset 0,msr,end ;check acknowledge from ;receiver ;if no acknowledge, end :transmission transmit lda databuf ;get the next byte of data tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-12 MC68HC05L28 i 2 c-bus 8 8.5.4 generation of a stop signal a data tr ansf er ends with a st op signal gener ated b y the master de vice . a master tr ansmitter can simply generate a stop signal after all the data has been transmitted; for example: mastx brset 0,msr,end ;if no acknowledgement, ;branch to end ldaa txcnt ;get value from the ;transmitting counter beq end ;if no more data, branch to end ldaa databuf ;get next byte of data staa mdr ;transmit the data dec txcnt ;decrease the txcnt bra emastx ;exit end bclr 5,mcr ;generate a stop condition emastx rti ;return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not ackno wledging the last b yte of data. this can be done b y setting the tr ansmit ac kno wledge bit (txak) before reading the second last byte of data. before reading the last byte of data, a stop signal m ust be gener ated ?rst. the f ollo wing is an e xample sho wing ho w a st op signal is generated by a master receiver. masr dec rxcnt beq enmasr ;last byte to be read lda rxcnt deca ;check second last byte to be ;read bne nxmar ;not last one or second last lamar bset 3,mcr ;second last, disable ;acknowledgement transmitting bra nxmar ;nxmar enmasr bclr 5,mcr ;last one, generate stop signal nxmar lda mdr ;read data and store sta rxbuf rti 8.5.5 generation of a repeated start signal at the end of the data tr ansfer , if the master still w ants to comm unicate on the b us , it can gener ate another start signal, followed by another slave address , without ?rst gener ating a stop signal. for example: tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-13 i 2 c-bus 8 restart bclr 5,mcr ;another start (restart) is ;generated by bset 5,mcr ;these two consecutive ;instructions ldaa calling ;get the calling address staa mdr ;transmit the calling address 8.5.6 slave mode in the slave interrupt service routine , the maas bit should be tested to chec k if a calling of its o wn address has just been receiv ed. if maas is set, softw are should set the tr ansmit/receiv e mode select bit (mtx) according to the r/w command bit, sr w. wr iting to the mcr clears the maas bit automatically . a data tr ansf er ma y then be initiated b y wr iting to mdr or b y perf or ming a dumm y read from mdr. in the sla v e tr ansmitter routine , the receiv ed ac kno wledge bit (rxak) m ust be tested bef ore tr ansmitting the ne xt b yte of data. if rxak is set, this means an end of data signal from the master receiv er , which m ust then s witch from tr ansmitter mode to receiv er mode b y softw are . this is f ollo wed b y a dumm y read, which releases the scl line so that the master can gener ate a st op signal. 8.5.7 arbitration lost only one master can engage the de vice at one time . those de vices wishing to engage the b us , b ut ha ving lost arbitr ation, are immediately s witched to sla v e receiv e mode b y hardw are . their data output to the sd a line is stopped, b ut the inter nal tr ansmitting cloc k is still gener ated until the end of the b yte dur ing which arbitr ation w as lost. an interr upt occurs at the f alling edge of the ninth cloc k of this tr ansf er with mal = 1 and mst a = 0. if one master attempts to star t tr ansmission while the b us is being engaged b y another master , the hardw are inhibits the tr ansmission; the mst a bit is cleared without gener ating a st op condition, an interr upt is gener ated, and mal is set to indicate that the attempt to engage the b us has f ailed. in these cases , the sla v e interr upt ser vice routine should test mal ?rst; if mal is set, it should be cleared b y softw are . 8.5.8 operation during stop and wait modes during stop mode, the i 2 c-bus is disabled. during wait mode , the i 2 c-b us is idle , but wak es up when it receiv es a v alid star t condition in slave mode. if the interrupt is enabled, the cpu comes out of wait mode after the end of a byte of transmission. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-14 MC68HC05L28 i 2 c-bus 8 figure 8-3 example of a typical i 2 c-bus interrupt routine clear mif set txak = 1 master mode? last byte transmitted? generate stop signal write next byte to mdr read data from mdr and store second last byte to be read? generate stop signal tx/ rx? rxak = 0? last byte to be read? rti a yes no yes yes yes yes no no no no rx tx tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 8-15 i 2 c-bus 8 figure 8-3 example of a typical i 2 c-bus interrupt routine (continued) tx next byte maas = 1? set rx mode write to mdr switch to rx mode ack from receiver? read mdr and store maas = 1? srw = 1? tx / rx? rti yes no rx yes no clear mal set tx mode dummy read from mdr dummy read from mdr arbitration lost? a no tx yes yes no no yes tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8-16 MC68HC05L28 i 2 c-bus 8 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 9-1 a/d converter 9 9 a/d converter the analog to digital con ver ter system consists of a single 8-bit successiv e appro ximation conver ter and a 16-channel m ultiplexer . there are only tw o a/d channels a vailab le on the MC68HC05L28. these are connected to the adx pins of the MC68HC05L28 and the other channels are dedicated to inter nal ref erence points f or test functions . the adx pins do not ha ve any inter nal output dr iver circuitr y connected to them because this circuitr y w ould load the analog input signal due to output buffer leakage current. there is one 8-bit result data register, addata and one 8-bit status/control register, adstat. the a/d con ver ter is r atiometr ic and tw o dedicated pins , vrefh and vrefl, are used to supply the ref erence v oltage le v els of each analog input. these pins are used in pref erence to the system po wer supply lines because an y v oltage drops in the bonding wires of the hea vily loaded supply pins could degr ade the accur acy of the a/d con v ersion. an input v oltage equal to or g reater than v refh con verts to $ff (full scale) with no o v er?o w indication and an input v oltage equal to v refl con ver ts to $00. the a/d con ver ter can oper ate from either the b us cloc k or an inter nal rc type oscillator . the inter nal rc type oscillator is activ ated b y the adrc bit in adst a t and can be used to giv e a suf?ciently high clock r ate to the a/d con ver ter when the b us speed is too lo w to provide accurate results (see section 9.2.1.2). when the a/d con ver ter is not being used it can be disconnected, using the adon bit in the adstat register, in order to save power (see section 9.2.1.3). 9.1 a/d converter operation the a/d con ver ter consists of an analog m ultiplexer , an 8-bit digital to analog capacitor arr ay, a comparator and a successive approximation register (sar) (see figure 9-1). there are f our options that can be selected b y the m ultiplexer ; the adx input pin, vrh, (vrh+vrl)/2 or vrl. selection is made via the chx bits in the adst a t register (see section 9.2.1.4). adx are the only input points f or a/d con v ersion oper ations; the others are reference points which can be used for test purposes. the a/d ref erence input (adx) is applied to a precision inter nal digital to analog con ver ter . control logic driv es this d/a con ver ter and the analog output is successiv ely compared with the analog input (adx) sampled at the beginning of the con v ersion. the con v ersion is monotonic with no missing codes . tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 9-2 MC68HC05L28 a/d converter 9 the result of each successiv e compar ison is stored in the sar and, when the con v ersion is complete, the contents of the sar are transferred to the read-only result data register ($17), and the conversion complete ?ag, coco, is set in the a/d status/control register ($15). note: any wr ite to the a/d status/control register will abor t the current con version, reset the conversion complete ?ag and start a new conversion on the selected channel. at po w er-on or e xter nal reset, both the adrc and adon bits are cleared, thus the a/d is disab led. figure 9-1 a/d converter block diagram ad0 vrh (vrh+vrl)/2 vrl analog mux a/d result data register (addata) successive approximation register and control 8-bit capacitive dac with sample and hold vrh vrl result a/d status/control register (adstat) (channel assignment) coco adrc adon ch3 ch2 ch1 ch0 ad1 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 9-3 a/d converter 9 9.2 a/d registers 9.2.1 a/d status/control register (adstat) 9.2.1.1 coco conversion complete ?ag 1 (set) C coco ?ag is set each time a conversion is complete, allowing the new result to be read from the a/d result data register ($16). the converter then starts a new conversion. 0 (clear) C coco is cleared b y reading the result data register or wr iting to the status/control register. reset clears the coco ?ag. 9.2.1.2 adrc a/d rc oscillator control the adrc bit allo ws the user to control the a/d rc oscillator , which is used to pro vide a suf?ciently high clock rate to the a/d to ensure accuracy when the chip is running at low speeds. 1 (set) C when the adrc bit is set, the a/d rc oscillator is tur ned on and, if adon is set, the a/d r uns from the rc oscillator cloc k. see table 9-1. 0 (clear) C when the adrc bit is cleared, the a/d rc oscillator is turned-off and, if adon is set, the a/d runs from the cpu clock. when the a/d rc oscillator is tur ned on, it tak es time t adrc to stabiliz e (see section 12.4). during this time a/d conversion results may be inaccurate. power-on or external reset clears the adrc bit. 9.2.1.3 adon a/d converter on the adon bit allows the user to enable/disable the a/d converter. 1 (set) C a/d converter is switched on. 0 (clear) C a/d converter is switched off. when the a/d con ver ter is s witched on, it tak es time t adon f or the current sources to stabiliz e (see section 12.4). during this time a/d conversion results may be inaccurate. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control register (adstat) $0015 coco adrc adon ch3 ch2 ch1 ch0 0000 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 9-4 MC68HC05L28 a/d converter 9 power-on or external reset will clear the adon bit, disabling the a/d converter. 9.2.1.4 ch3 C ch0 a/d channels 3, 2, 1 and 0 the ch3Cch0 bits allow the user to determine which channel of the a/d converter multiplexer is selected. see table 9-2 for channel selection. reset clears these bits. table 9-1 a/d clock selection adrc adon rc oscillator a/d converter comments 0 0 off off a/d switched off. 0 1 off on a/d using cpu clock. 1 0 on off allows the rc oscillator to stabilise. 1 1 on on a/d using rc oscillator clock. table 9-2 a/d channel assignment ch3 ch2 ch1 ch0 channel selected 0 0 0 0 ad0 0 0 0 1 ad1 0 0 1 0 reserved 0 0 1 1 reserved 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 vrh pin (high) 1 0 0 1 (vrh + vrl) / 2 1 0 1 0 vrl pin (low) 1 0 1 1 vrl pin (low) 1 1 0 0 vrl pin (low) 1 1 0 1 vrl pin (low) 1 1 1 0 vrl pin (low) 1 1 1 1 vrl pin (low) tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 9-5 a/d converter 9 9.2.2 a/d input register (adin) the adin register allo ws the a/d input to be read as a static input. reading this register dur ing an a/d con v ersion sequence ma y inject noise into the analog input and reduce the accur acy of the a/d result. note: perfor ming a digital read of the a/d input with le v els other than v dd or v ss on the adin pin will result in g reater po w er dissipation dur ing the read cycle . this will also giv e unpredictable results on the adin input. reset does not affect the adin bit. 9.2.3 a/d result data register ( addata ) addata is a read-only register which is used to store the result of an a/d conversion. the result is loaded into the register from the sar and the con v ersion complete ?ag in the adst at register, coco, is set. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d input register (adin) $0016 ad1 ad0 unde?ned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d result data register (addata) $0017 unde?ned tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 9-6 MC68HC05L28 a/d converter 9 9.3 adx analog input the exter nal analog v oltage v alue to be processed b y the a/d con ver ter is sampled on an inter nal capacitor through a resistive path, provided by input-selection s witches and a sampling aper ture time s witch, as sho wn in figure 9-2. sampling time is limited to 12 b us cloc k cycles . after sampling, the analog v alue is stored on the capacitor and held until the end of con version. during this hold time , the analog input is disconnected from the inter nal a/d system and the e xternal voltage source sees a high impedance input. the equiv alent analog input dur ing sampling is an rc lo w-pass ?lter with a minim um resistance of 50 k? and a capacitance of at least 10pf (these are typical v alues measured at room temperature). figure 9-2 electrical model of an a/d input pin analog input pin input protection device v rl < 2pf + ~20v - ~0.7v 400 na junction leakage 50k? 10pf dac capacitance note: the analog switch is closed during the 12 cycle sample time only. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 10-1 resets and interrupts 10 10 resets and interrupts 10.1 resets the MC68HC05L28 can be reset in three w ays: b y the initial po w er-on reset function, b y an activ e lo w input to the reset pin and b y a cop w atchdog timer reset, if the w atchdog timer is enab led. 10.1.1 power-on reset a po w er-on reset occurs when a positiv e tr ansition is detected on vdd . the po w er-on reset function is str ictly f or po w er tur n-on conditions and should not be used to detect drops in the po wer supply v oltage . the po w er-on circuitr y pro vides a stabilization dela y (t porl ) from when the oscillator becomes activ e . if the e xternal reset pin is lo w at the end of this dela y then the processor remains in the reset state until reset goes high. the user m ust ensure that the v oltage on vdd has risen to a point where the mcu can operate properly by the time t porl has elapsed. if there is doubt, the e xternal reset pin should remain lo w until the v oltage on vdd has reached the speci?ed minim um oper ating v oltage . this ma y be accomplished b y connecting an e xternal rc-circuit to this pin to gener ate a pow er-on reset (por). in this case , the time constant must be great enough (at least 100ms) to allow the oscillator circuit to stabilise. 10.1.2 reset pin when the oscillator is r unning in a stab le state , the mcu is reset when a logic z ero is applied to the reset input for a minimum per iod of 1.5 machine cycles (t cyc ). this pin contains an inter nal schmitt trigger as part of its input to improve noise immunity. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 10-2 MC68HC05L28 resets and interrupts 10 10.1.3 computer operating properly (cop) reset the mcu contains a w atchdog timer that automatically times out if not reset (cleared) within a speci?c time by a program reset sequence. note: cop timeout is prevented by periodically writing a 0 to bit 0 of address $3ff0. if the cop watchdog timer is allowed to timeout, an internal reset is generated to reset the mcu. because the inter nal reset signal is used, the mcu comes out of a cop reset in the same operating mode it was in when the cop timeout was generated. the cop reset function is enabled or disabled by a bit in the option register. see section 5.2 for more information on the cop watchdog timer. 10.2 interrupts the mcu can be interr upted b y diff erent sources C six maskab le hardw are interr upts and one non-maskable software interrupt: ? external signal on the irq pins ( irq0, irq1, irq2) ? core timer ? 16-bit programmable timer ? i 2 c ? software interrupt instruction (swi) interr upts cause the processor to sa v e the register contents on the stac k and to set the interr upt mask (i-bit) to prevent additional interrupts. the rti instruction (return from interrupt) causes the register contents to be recovered from the stack and normal processing to resume. unlike reset, hardware interr upts do not cause the current instr uction ex ecution to be halted, b ut are considered pending until the current instr uction is complete . the current instr uction is the one already f etched and being oper ated on. when the current instr uction is complete , the processor chec ks all pending hardw are interr upts . if interr upts are not mask ed (ccr i-bit clear) and the corresponding interr upt enab le bit is set, the processor proceeds with interr upt processing; otherwise, the next instruction is fetched and executed. table 10-1 shows the relative prior ity of all the possib le interrupt sources. figure 10-1 shows the interrupt processing ?ow. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 10-3 resets and interrupts 10 10.2.1 non-maskable software interrupt (swi) the softw are interr upt (swi) is an e xecutab le instr uction and a non-maskab le interr upt: it is ex ecuted regardless of the state of the i-bit in the ccr. if the i-bit is z ero (interrupts enabled), swi is e x ecuted after interr upts that w ere pending when the swi w as f etched, b ut bef ore interr upts gener ated after the swi w as f etched. the swi interr upt ser vice routine address is speci?ed b y the contents of memory locations $3ffc and $3ffd. 10.2.2 maskable hardware interrupts if the interr upt mask bit (i-bit) of the ccr is set, all maskab le interrupts (internal and external) are masked. clearing the i-bit allows interrupt processing to occur. note: the inter nal interr upt latch is cleared in the ?rst par t of the interr upt ser vice routine; therefore , one e xter nal interr upt pulse could be latched and ser viced as soon as the i-bit is cleared. table 10-1 interrupt priorities source register flags vector address priority reset $3ffe, $3fff highest software interrupt (swi) $3ffc, $3ffd external interrupt ( irq) irqx irqxint $3ffa, $3ffb core timer ctcsr ctof, rtif $3ff8, $3ff9 i 2 c msr mif $3ff6, $3ff7 programmable timer tsr icf, ocf, tof $3ff4, $3ff5 lowest tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 10-4 MC68HC05L28 resets and interrupts 10 figure 10-1 interrupt ?ow chart i 2 c interrupt? core timer interrupt? swi instruction ? from reset fetch next instruction execute instruction restore registers from stack: cc, a, x, pc set i-bit no no no no no no no yes yes yes yes yes yes yes timer16 interrupt? external interrupt? irq0,1,2 clear irq0,1,2 load pc from: swi: irq0: irq1: irq2: ctimer: i 2 c: tim16: stack pc, x, a, cc rti instruction ? $3ffc - $3ffd $3ffa - $3ffb $3ffa - $3ffb $3ffa - $3ffb $3ff8 - $3ff9 $3ff6 - $3ff7 $3ff4 - $3ff5 is i-bit set? tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 10-5 resets and interrupts 10 10.2.2.1 external interrupt ( irq0, irq1, irq2) these external interrupt sources use the same interrupt vector ($3ffa, $3ffb) irq0 if the interr upt mask bit (i-bit) of the ccr is set, all maskab le interrupts (internal and external) are disab led. clear ing the i-bit enab les interr upts . the interr upt request is latched immediately following the falling edge of irq0. it is then synchronized internally and serviced by the interrupt service routine located at the address speci?ed by the contents of $3ffa and $3ffb. either a le vel-sensitiv e and edge-sensitiv e tr igger , or an edge-sensitiv e-only tr igger can be selected b y bit-1 (irqed) in the option register ($1d). when irqed is cleared, the interr upt is edge-and-lev el sensitiv e and when set the interr upt is edge sensitiv e. irqed can be wr itten to once only after a power-on-reset or external reset. this bit is cleared after reset. irq1 this interr upt can be enab led independently and diff erent sensitivities can be de?ned: f alling edge , f alling edge and lo w le v el, r ising edge , r ising edge and high le v el. the interr upt is enab led b y setting bit 4 (irq1ena) of register $0a and is disab led by clearing it. the interrupt vector, $3ffa and $3ffb , is shared with the other irq interr upts . bit 5 of register $0a is an interr upt ?ag (irq1int) which distinguishes betw een the interr upts and is set when an interr upt occurs . the interr upt is cleared b y wr iting 1 to the irq1rst bit which alw a ys reads 0. the status of irq1 can be monitored by reading the irq1val bit (bit 0 on the irq1 register). irq1int irq1 interrupt ?ag 1 (set) C a valid irq1 interrupt has been generated. 0 (clear) C no valid irq1 interrupt has been generated. irq1ena irq1 interrupt enable 1 (set) C irq1 interrupts are enabled. 0 (clear) C irq1 interrupts are disabled. irq1lv, irq1edg irq1 interrupt sensitivity bits these tw o bits are used to select the sensitivity of the irq1 interr upt tr igger according to table 10-2. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset irq1 status/control register (irq1) $000a irq1int irq1ena irq1lv irq1edg irq1rst irq1val ??00 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 10-6 MC68HC05L28 resets and interrupts 10 irq1rst irq1 reset the irq1 interr upt is cleared b y wr iting a 1 to this bit. this bit is wr ite-only and alw ays returns zero. irq1val irq1 pin status the irq1val bit re?ects current status of the irq1 pin. irq2 this interr upt can be enab led independently and diff erent sensitivities can be de?ned: f alling edge , falling edge and low level, rising edge, rising edge and high level. the interrupt is enabled by setting bit 4 (irq2ena) of register $0b and is disab led by clear ing it. the interr upt vector, $3ffa and $3ffb, s shared with the other irq interrupts. bit 5 of register $0b is an interrupt ?ag (irq2int) which distinguishes between the interrupts and is set when an interrupt occurs. the interr upt is cleared b y wr iting 1 to the irq2rst bit which alw a ys reads 0. the status of irq2 can be monitored by reading the irq2val bit (bit 0 on the irq2 register). irq2int irq2 interrupt ?ag 1 (set) C a valid irq2 interrupt has been generated. 0 (clear) C no valid irq2 interrupt has been generated. irq2ena irq2 interrupt enable 1 (set) C irq2 interrupts are enabled. 0 (clear) C irq2 interrupts are disabled. irq2lv, irq2edg irq2 interrupt sensitivity bits these tw o bits are used to select the sensitivity of the irq2 interr upt tr igger according to table 10-2. table 10-2 irq1 interrupt sensitivity irq1lv irq1edg interrupt sensitivity 0 0 falling edge 0 1 rising edge 1 0 falling edge and low level 1 1 rising edge and high level address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset irq2 status/control register (irq2) $000b irq2int irq2ena irq2lv irq2edg irq2rst irq2val ??00 0000 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 10-7 resets and interrupts 10 irq2rst irq2 reset the irq2 interr upt is cleared b y wr iting a 1 to this bit. this bit is wr ite-only and alw ays returns zero. irq2val irq2 pin status the irq2val bit re?ects current status of the irq2 pin. 10.2.2.2 real time and core timer (ctimer) interrupts there are tw o core timer interr upt ?ags that cause a ctimer interr upt whenev er an interr upt is enab led and its ?ag becomes set (r tif and ct of). the interr upt ?ags and enab le bits are located in the ctimer control and status register (ctcsr). these interr upts v ector to the same interr upt ser vice routine , whose star t address is contained in memor y locations $3ff8 and $3ff9 (see section 5.3.1 and figure 5-1). to mak e use of the real time interr upt the rtie bit must ?rst be set. the rtif bit will then be set after the speci?ed number of counts. to mak e use of the core timer o ver?ow interr upt, the ct ofe bit m ust ?rst be set. the ct of bit will then be set when the core timer counter register over?ows from $ff to $00. 10.2.2.3 programmable 16-bit timer interrupt there are ?v e interr upt ?ags that cause a timer interr upt when set and enab led. the timer interr upt enab le bits are located in the timer control registers (tcr) and the timer interr upt ?ags are located in the timer status registers (tsr). all interr upts v ector to the same ser vice routine , whose star t address is contained in memory locations $3ff4 and $3ff5. in wait mode the cpu clock halts but the timer continues to run. table 10-3 irq2 interrupt sensitivity irq2lv irq2edg interrupt sensitivity 0 0 falling edge 0 1 rising edge 1 0 falling edge and low level 1 1 rising edge and high level tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 10-8 MC68HC05L28 resets and interrupts 10 10.2.2.4 i 2 c interrupts there is an interr upt ?ag and three status ?ags f or the i 2 c that cause an i 2 c interr upt when set and enab led. these interr upts will v ector to the ser vice routine located at the address speci?ed b y the contents of memory locations $3ff6 and $3ff7. 10.2.3 hardware controlled interrupt sequence the following three functions (reset, stop, and wait) are not in the strictest sense interrupts. however, the y are acted upon in a similar manner . flowcharts for stop and wait are shown in section 2-5 and figure 2-6. reset: a reset condition causes the prog r am to v ector to its star ting address , which is contained in memor y locations $3ffe (msb) and $3fff (lsb). the i-bit in the condition code register is also set, to disable maskable interrupts. stop: the st op instr uction causes the oscillator to be tur ned off and the processor to sleep until an external interrupt ( irq) interrupt occurs, or the device is reset. wait: the wait instr uction causes all processor cloc ks to stop , but leav es the core timer clock r unning. this rest state of the processor can be cleared b y reset, an external interr upt ( irq ), or a timer interr upt. there are no special w ait v ectors f or these interrupts. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-1 cpu core and instruction set 11 11 cpu core and instruction set this section pro vides a descr iption of the cpu core registers , the instr uction set and the addressing modes of the MC68HC05L28. 11.1 registers the mcu contains ?v e registers , as sho wn in the prog r amming model of figure 11-1. the interrupt stacking order is shown in figure 11-2. 11.1.1 accumulator (a) the accum ulator is a gener al pur pose 8- bit register used to hold oper ands and results of arithmetic calculations or data manipulations. figure 11-1 programming model accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 7 0 7 0 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 7 0 1 1 1 h i n z c 0 0 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-2 MC68HC05L28 cpu core and instruction set 11 11.1.2 index register (x) the inde x register is an 8- bit register , which can contain the inde x ed addressing v alue used to create an effective address. the index register may also be used as a temporary storage area. 11.1.3 program counter (pc) the prog r am counter is a 16- bit register , which contains the address of the ne xt b yte to be f etched. although the m68hc05 cpu core can address 64k b ytes of memor y , the actual address r ange of the MC68HC05L28 is limited to 16k b ytes . the tw o most signi?cant bits of the prog ram counter are therefore not used and are permanently set to zero. 11.1.4 stack pointer (sp) the stac k pointer is a 16- bit register , which contains the address of the ne xt free location on the stack. dur ing an mcu reset or the reset stac k pointer (rsp) instr uction, the stac k pointer is set to location $00ff . the stac k pointer is then decremented as data is pushed onto the stac k and incremented as data is pulled from the stack. when accessing memor y , the ten most signi?cant bits are per manently set to 0000000011. these ten bits are appended to the six least signi?cant register bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts ma y use up to 64 (decimal) locations . if 64 locations are e xceeded, the stac k pointer wr aps around and o verwr ites the pre viously stored infor mation. a subroutine call occupies tw o locations on the stac k; an interr upt uses ?v e locations. 11.1.5 condition code register (ccr) the ccr is a 5- bit register in which f our bits are used to indicate the results of the instr uction just ex ecuted, and the ?fth bit indicates whether interr upts are mask ed. these bits can be individually tested b y a prog r am, and speci?c actions can be tak en as a result of their state . each bit is explained in the following paragraphs. figure 11-2 stacking order condition code register accumulator index register program counter high program counter low 7 0 stack unstack decreasing memory address increasing memory address interrupt return tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-3 cpu core and instruction set 11 half carry (h) this bit is set dur ing add and adc oper ations to indicate that a carr y occurred betw een bits 3 and 4. interrupt (i) when this bit is set, all maskab le interrupts are masked. if an interr upt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carr y or borro w out of the ar ithmetic logical unit (alu) occurred dur ing the last ar ithmetic oper ation. this bit is also aff ected dur ing bit test and br anch instructions and during shifts and rotates. 11.2 instruction set the mcu has a set of 62 basic instr uctions . the y can be g rouped into ?v e diff erent types as follows: C register/memory C read/modify/write C branch C bit manipulation C control the f ollo wing par agr aphs br ie?y e xplain each type . all the instr uctions within a giv en type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 11-1. tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-4 MC68HC05L28 cpu core and instruction set 11 11.2.1 register/memory instructions most of these instr uctions use tw o oper ands . the ?rst oper and is either the accum ulator or the index register . the second oper and is obtained from memor y using one of the addressing modes . the jump unconditional (jmp) and jump to subroutine (jsr) instr uctions ha v e no register operand. refer to table 11-2 for a complete list of register/memory instructions. 11.2.2 branch instructions these instr uctions cause the prog r am to br anch if a par ticular condition is met; otherwise , no operation is performed. branch instructions are two-byte instructions. refer to table 11-3. 11.2.3 bit manipulation instructions the mcu can set or clear any writable bit that resides in the ?rst 256 bytes of the memory space (page 0). all por t data and data direction registers , timer and ser ial interf ace registers , control/status registers and a por tion of the on-chip ram reside in page 0. an additional f eature allo ws the softw are to test and br anch on the state of an y bit within these locations . the bit set, bit clear , bit test and br anch functions are all implemented with single instr uctions. f or the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 11-4. 11.2.4 read/modify/write instructions these instructions read a memory location or a register, modify or test its contents, and write the modi?ed value bac k to memor y or to the register . the test f or negativ e or z ero (tst) instr uction is an e xception to this sequence of reading, modifying and wr iting, since it does not modify the v alue. refer to table 11-5 for a complete list of read/modify/write instructions. 11.2.5 control instructions these instr uctions are register ref erence instr uctions and are used to control processor oper ation during program execution. refer to table 11-6 for a complete list of control instructions. 11.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instr uctions (see t able 11-7), and an opcode map f or the instr uction set of the m68hc05 mcu family (see table 11-8). tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-5 cpu core and instruction set 11 table 11-1 mul instruction operation x:a ? x*a description multiplies the eight bits in the index register by the eight bits in the accum ulator and places the 16- bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 11-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b7 2 4 c7 3 5 f7 1 4 e7 2 5 d7 3 6 store x in memory stx bf 2 4 cf 3 5 ff 1 4 ef 2 5 df 3 6 add memory to a add ab 2 2 bb 2 3 cb 3 4 fb 1 3 eb 2 4 db 3 5 add memory and carry to a adc a9 2 2 b9 2 3 c9 3 4 f9 1 3 e9 2 4 d9 3 5 subtract memory sub a0 2 2 b0 2 3 c0 3 4 f0 1 3 e0 2 4 d0 3 5 subtract memory from a with borrow sbc a2 2 2 b2 2 3 c2 3 4 f2 1 3 e2 2 4 d2 3 5 and memory with a and a4 2 2 b4 2 3 c4 3 4 f4 1 3 e4 2 4 d4 3 5 or memory with a ora aa 2 2 ba 2 3 ca 3 4 fa 1 3 ea 2 4 da 3 5 exclusive or memory with a eor a8 2 2 b8 2 3 c8 3 4 f8 1 3 e8 2 4 d8 3 5 arithmetic compare a with memory cmp a1 2 2 b1 2 3 c1 3 4 f1 1 3 e1 2 4 d1 3 5 arithmetic compare x with memory cpx a3 2 2 b3 2 3 c3 3 4 f3 1 3 e3 2 4 d3 3 5 bit test memory with a (logical compare) bit a5 2 2 b5 2 3 c5 3 4 f5 1 3 e5 2 4 d5 3 5 jump unconditional jmp bc 2 2 cc 3 3 fc 1 2 ec 2 3 dc 3 4 jump to subroutine jsr bd 2 5 cd 3 6 fd 1 5 ed 2 6 dd 3 7 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-6 MC68HC05L28 cpu core and instruction set 11 table 11-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 11-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0C7) 2?n 3 5 branch if bit n is clear brclr n (n=0C7) 01+2?n 3 5 set bit n bset n (n=0C7) 10+2?n 2 5 clear bit n bclr n (n=0C7) 11+2?n 2 5 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-7 cpu core and instruction set 11 table 11-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c 1 3 5c 1 3 3c 2 5 7c 1 5 6c 2 6 decrement dec 4a 1 3 5a 1 3 3a 2 5 7a 1 5 6a 2 6 clear clr 4f 1 3 5f 1 3 3f 2 5 7f 1 5 6f 2 6 complement com 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 negate (twos complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 logical shift left lsl 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst 4d 1 3 5d 1 3 3d 2 4 7d 1 4 6d 2 5 multiply mul 42 1 11 table 11-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-8 MC68HC05L28 cpu core and instruction set 11 table 11-7 instruction set mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc ? add ? and ? ? ? asl ? ? asr ? ? bcc ? ? ? ? ? bclr ? ? ? ? ? bcs ? ? ? ? ? beq ? ? ? ? ? bhcc ? ? ? ? ? bhcs ? ? ? ? ? bhi ? ? ? ? ? bhs ? ? ? ? ? bih ? ? ? ? ? bil ? ? ? ? ? bit ? ? ? blo ? ? ? ? ? bls ? ? ? ? ? bmc ? ? ? ? ? bmi ? ? ? ? ? bms ? ? ? ? ? bne ? ? ? ? ? bpl ? ? ? ? ? bra ? ? ? ? ? brn ? ? ? ? ? brclr ? ? ? ? brset ? ? ? ? bset ? ? ? ? ? bsr ? ? ? ? ? clc ? ? ? ? 0 cli ? 0 ? ? ? clr ? ? 0 1 ? cmp ? ? condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-9 cpu core and instruction set 11 com ? ? 1 cpx ? ? dec ? ? ? eor ? ? ? inc ? ? ? jmp ? ? ? ? ? jsr ? ? ? ? ? lda ? ? ? ldx ? ? ? lsl ? ? lsr ? ? 0 mul 0 ? ? ? 0 neg ? ? nop ? ? ? ? ? ora ? ? ? rol ? ? ror ? ? rsp ? ? ? ? ? rti ? ? ? ? ? rts ? ? ? ? ? sbc ? ? sec ? ? ? ? 1 sei ? 1 ? ? ? sta ? ? ? stop ? 0 ? ? ? stx ? ? ? sub ? ? swi ? 1 ? ? ? tax ? ? ? ? ? tst ? ? ? txa ? ? ? ? ? wait ? 0 ? ? ? table 11-7 instruction set (continued) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-10 MC68HC05L28 cpu core and instruction set 11 table 11-8 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0 1 2 3 4 5 6 7 8 9 a b c d e f high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 5 5 3 5 3 3 6 5 9 2 3 4 5 4 3 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 1 0001 5 5 3 6 2 3 4 5 4 3 1 0001 brclr0 bclr0 brn rts cmp cmp cmp cmp cmp cmp 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 2 0010 5 5 3 11 2 3 4 5 4 3 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 3 0011 5 5 3 5 3 3 6 5 10 2 3 4 5 4 3 3 0011 brclr1 bclr1 bls com coma comx com com swi cpx cpx cpx cpx cpx cpx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 4 0100 5 5 3 5 3 3 6 5 2 3 4 5 4 3 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 5 0101 5 5 3 2 3 4 5 4 3 5 0101 brclr2 bclr2 bcs bit bit bit bit bit bit 3 btb 2 bsc 2 rel 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 6 0110 5 5 3 5 3 3 6 5 2 3 4 5 4 3 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 7 0111 5 5 3 5 3 3 6 5 2 4 5 6 5 4 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 8 1000 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix 9 1001 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix a 1010 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix b 1011 5 5 3 2 2 3 4 5 4 3 b 1011 brclr5 bclr5 bmi sei add add add add add add 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix c 1100 5 5 3 5 3 3 6 5 2 2 3 4 3 2 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix d 1101 5 5 3 4 3 3 5 4 2 6 5 6 7 6 5 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 5 5 3 2 2 3 4 5 4 3 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3 btb 2 bsc 2 rel 1 inh 2 imm 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 5 5 3 5 3 3 6 5 2 2 4 5 6 5 4 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3 btb 2 bsc 2 rel 2 dir 1 inh 1 inh 2 ix1 1 ix 1 inh 1 inh 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 3 0 0000 sub 1 ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-11 cpu core and instruction set 11 11.3 addressing modes ten different addressing modes provide programmers with the ?exibility to optimize their code for all situations. the various indexed addressing modes make it possib le to locate data tab les, code conversion tab les and scaling tab les an ywhere in the memor y space. short index ed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or tw o b yte direct addressing instr uctions access all data b ytes in most applications . extended addressing permits jump instructions to reach all memory locations. the ter m eff ectiv e address (ea) is used in descr ibing the v ar ious addressing modes . the effectiv e address is de?ned as the address from which the argument f or an instruction is fetched or stored. the ten addressing modes of the processor are descr ibed below. p arentheses are used to indicate contents of the location or register ref erred to . f or e xample , (pc) indicates the contents of the location pointed to b y the pc (prog r am counter). an arro w indicates is replaced b y and a colon indicates concatenation of tw o b ytes . f or additional details and g raphical illustrations , ref er to the m6805 hmos/m146805 cmos f amil y micr ocomputer/ microprocessor user's manual or to the m68hc05 applications guide . 11.3.1 inherent in the inherent addressing mode , all the inf or mation necessar y to e x ecute the instr uction is contained in the opcode. operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 11.3.2 immediate in the immediate addressing mode , the oper and is contained in the b yte immediately f ollowing the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc ? pc+2 11.3.3 direct in the direct addressing mode, the effectiv e address of the argument is contained in a single b yte follo wing the opcode b yte . direct addressing allo ws the user to directly address the lo w est 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-12 MC68HC05L28 cpu core and instruction set 11 11.3.4 extended in the e xtended addressing mode , the eff ectiv e address of the argument is contained in the tw o b ytes f ollo wing the opcode b yte . instr uctions with e xtended addressing mode are capab le of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assemb ler , the user need not specify whether an instr uction uses direct or e xtended addressing. the assembler automatically selects the short form of the instruction. ea = (pc+1):(pc+2); pc ? pc+3 address bus high ? (pc+1); address bus low ? (pc+2) 11.3.5 indexed, no offset in the index ed, no offset addressing mode , the effectiv e address of the argument is contained in the 8-bit index register. this addressing mode can access the ?rst 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc ? pc+1 address bus high ? 0; address bus low ? x 11.3.6 indexed, 8-bit offset in the inde x ed, 8-bit offset addressing mode , the eff ectiv e address is the sum of the contents of the unsigned 8-bit inde x register and the unsigned b yte f ollo wing the opcode . theref ore the oper and can be located an ywhere within the lo w est 511 memor y locations . this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc ? pc+2 address bus high ? k; address bus low ? x+(pc+1) where k = the carry from the addition of x and (pc+1) 11.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit inde x register and the tw o unsigned bytes following the opcode. this address mode can be used in a manner similar to inde x ed, 8-bit offset e xcept that this three-b yte instr uction allows tab les to be an ywhere in memor y . as with direct and e xtended addressing, the motorola assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc ? pc+3 address bus high ? (pc+1)+k; address bus low ? x+(pc+2) where k = the carry from the addition of x and (pc+2) tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 11-13 cpu core and instruction set 11 11.3.8 relative the relativ e addressing mode is only used in br anch instr uctions . in relativ e addressing, the contents of the 8-bit signed b yte (the offset) f ollo wing the opcode are added to the pc if , and only if, the br anch conditions are tr ue. otherwise , control proceeds to the ne xt instr uction. the span of relativ e addressing is from C126 to +129 from the opcode address . the prog r ammer need not calculate the offset when using the motorola assemb ler , since it calculates the proper offset and checks to see that it is within the span of the branch. ea = pc+2+(pc+1); pc ? ea if branch taken; otherwise ea = pc ? pc+2 11.3.9 bit set/clear in the bit set/clear addressing mode , the bit to be set or cleared is par t of the opcode . the b yte follo wing the opcode speci?es the address of the b yte in which the speci?ed bit is to be set or cleared. any read/wr ite bit in the ?rst 256 locations of memor y , including i/o , can be selectiv ely set or cleared with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) 11.3.10 bit test and branch the bit test and br anch addressing mode is a combination of direct addressing and relativ e addressing. the bit to be tested and its condition (set or clear) is included in the opcode . the address of the b yte to be tested is in the single b yte immediately follo wing the opcode b yte (ea1). the signed relative 8-bit offset in the third b yte (ea2) is added to the pc if the speci?ed bit is set or cleared in the speci?ed memor y location. this single three-byte instruction allows the program to br anch based on the condition of an y readab le bit in the ?rst 256 locations of memor y . the span of br anch is from C125 to +130 from the opcode address . the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) ea2 = pc+3+(pc+2); pc ? ea2 if branch taken; otherwise pc ? pc+3 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 11-14 MC68HC05L28 cpu core and instruction set 11 this page left blank intentionally tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MC68HC05L28 motorola 12-1 electrical specifications 12 12 electrical specifications this section contains the electr ical speci?cations and associated timing inf or mation f or the MC68HC05L28. 12.1 maximum ratings note: this de vice contains circuitr y designed to protect against damage due to high electrostatic v oltages or electr ic ?elds . ho wever , it is recommended that nor mal precautions be tak en to a v oid the application of an y v oltages higher than those giv en in the maximum ratings tab le to this high impedance circuit. f or maximum reliability all unused inputs should be tied to either v ss or v dd . (1) all voltages are with respect to v ss . (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. table 12-1 maximum ratings rating symbol value unit supply voltage (1) v dd C 0.3 to +7.0 v input voltage: normal operations bootloader mode ( irq0 pin only) v in v ss C 0.3 to v dd + 0.3 v ss C 0.3 to 2xv dd + 0.3 v current sink into port b i b 80 ma operating temperature range MC68HC05L28 (standard) t a t l to t h -40 to +85 ?c storage temperature range t stg C 65 to +150 ?c current drain per pin (2) C excluding vdd and vss i d 25 ma tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 12-2 MC68HC05L28 electrical specifications 12 12.2 thermal characteristics and power considerations the aver age chip junction temper ature, t j , in deg rees celcius can be obtained from the f ollowing equation: [1] where: t a = ambient temperature (?c) q ja = package thermal resistance, junction-to-ambient (?c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ? v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: [2] solving equations [1] and [2] for k gives: [3] where k is a constant f or a particular par t. k can be deter mined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in table 12-2. table 12-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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